{"id":290,"date":"2018-03-13T13:38:40","date_gmt":"2018-03-13T05:38:40","guid":{"rendered":"http:\/\/www.max-shu.com\/blog\/?p=290"},"modified":"2018-03-13T13:38:40","modified_gmt":"2018-03-13T05:38:40","slug":"mini6410%e6%9d%bfuboot%e7%9a%84cpu_init-s","status":"publish","type":"post","link":"http:\/\/www.max-shu.com\/blog\/?p=290","title":{"rendered":"mini6410\u677fuboot\u7684cpu_init.S"},"content":{"rendered":"<p>#include &lt;config.h&gt;<br \/>\n#include &lt;s3c6410.h&gt;<\/p>\n<p>.globl mem_ctrl_asm_init<br \/>\nmem_ctrl_asm_init:<br \/>\nldr\u00a0\u00a0\u00a0\u00a0 r0, =ELFIN_MEM_SYS_CFG\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @Memory sussystem address 0x7e00f120<br \/>\nmov\u00a0\u00a0\u00a0\u00a0 r1, #0xd\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1\uff0c\u8fd9\u4e2a\u4e0d\u662f\u7531\u8fd9\u91cc\u51b3\u5b9a\uff0c<span style=\"color: #ff0000;\">\u8fd9\u91cc\u7684\u503c\u5e94\u8be5\u90fd\u88ab\u5ffd\u7565\uff1f<\/span><br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0]<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r0, =ELFIN_DMC1_BASE\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @DMC1 base address 0x7e001000<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =0x04<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_MEMC_CMD] \u00a0 \u00a0 \u00a0@\u8bbe\u7f6e\u5185\u5b58\u63a7\u5236\u5668\u4e3a\u914d\u7f6e\u72b6\u6001<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_DDR_REFRESH_PRD<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_REFRESH_PRD] \u00a0@\u8bbe\u7f6e\u5237\u65b0\u5468\u671f<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_DDR_CAS_LATENCY<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_CAS_LATENCY] \u00a0@\u8bbe\u7f6eCAS\u7b49\u5f85\u65f6\u95f4<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_DDR_t_DQSS<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_T_DQSS] \u00a0 \u00a0 \u00a0 \u00a0 \u00a0@\u8bbe\u7f6eDQS<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_DDR_t_MRD<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_T_MRD] \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0@\u8bbe\u7f6eMRD<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_DDR_t_RAS<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_T_RAS] \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0@\u8bbe\u7f6eRAS<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_DDR_t_RC<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_T_RC] \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0@\u8bbe\u7f6eRC<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_DDR_t_RCD<br \/>\nldr\u00a0\u00a0\u00a0\u00a0 r2, =DMC_DDR_schedule_RCD<br \/>\norr\u00a0\u00a0\u00a0\u00a0 r1, r1, r2<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_T_RCD] \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 @\u8bbe\u7f6eRCD<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_DDR_t_RFC<br \/>\nldr\u00a0\u00a0\u00a0\u00a0 r2, =DMC_DDR_schedule_RFC<br \/>\norr\u00a0\u00a0\u00a0\u00a0 r1, r1, r2<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_T_RFC] \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 @\u8bbe\u7f6eRFC<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_DDR_t_RP<br \/>\nldr\u00a0\u00a0\u00a0\u00a0 r2, =DMC_DDR_schedule_RP<br \/>\norr\u00a0\u00a0\u00a0\u00a0 r1, r1, r2<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_T_RP] \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0@\u8bbe\u7f6eRP<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_DDR_t_RRD<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_T_RRD] \u00a0 \u00a0 \u00a0 \u00a0 \u00a0@\u8bbe\u7f6eRRD<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_DDR_t_WR<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_T_WR] \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 @\u8bbe\u7f6eWR<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_DDR_t_WTR<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_T_WTR] \u00a0 \u00a0 \u00a0 \u00a0 @\u8bbe\u7f6eWTR<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_DDR_t_XP<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_T_XP] \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0@\u8bbe\u7f6eXP<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_DDR_t_XSR<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_T_XSR] \u00a0 \u00a0 \u00a0 \u00a0 \u00a0@\u8bbe\u7f6eXSR<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_DDR_t_ESR<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_T_ESR] \u00a0 \u00a0 \u00a0 \u00a0 \u00a0@\u8bbe\u7f6eESR<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC1_MEM_CFG<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_MEMORY_CFG] @\u8bbe\u7f6e\u5185\u5b58\u63a7\u5236\u5668\u914d\u7f6e\uff0c\u652f\u6301\u5355\u72ec\u7684CKE\u63a7\u5236\uff0c\u652f\u63011\u7247\u82af\u7247\uff0c\u652f\u6301\u8109\u51b24\uff0c\u884c\u5730\u5740\u6570\u4e3a13\u4f4d\uff0813\u4f4d\u5730\u5740\u4e3a128M\uff0c14\u4f4d\u5730\u5740\u5219\u4e3a256M\uff09\uff0c\u5217\u5730\u5740\u4e3a10\u4f4d\u3002<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC1_MEM_CFG2<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_MEMORY_CFG2] @\u8bfb\u5ef6\u65f61\u5468\u671f\uff0c\u79fb\u52a8DDR SDRAM\uff0c32\u4f4d\u5bbd\u5ea6\uff0c2\u4f4d\u9875\u5730\u5740\uff0cAXI\u65f6\u949f\u548c\u5185\u5b58\u65f6\u949f\u540c\u6b65\u3002<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC1_CHIP0_CFG<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_CHIP_0_CFG] \u00a0 \u00a0@\u9875\uff0d\u884c\uff0d\u5217\u7ed3\u6784\uff0c\u82af\u7247\u53ca\u5730\u5740\u4f4d\u9009\u62e9\uff0c\u5730\u5740\u4e3a0x50000000\u52300x60000000\uff08\u62160x58000000\uff09\uff0c\u5171256MB(\u6216128MB)<\/p>\n<p>ldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_DDR_32_CFG<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_USER_CONFIG] @DQS\u5ef6\u65f6\u8bbe\u7f6e\u4e3a0<\/p>\n<p>@DMC0 DDR Chip 0 configuration direct command reg<br \/>\nldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_NOP0<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_DIRECT_CMD] \u00a0@\u5148\u505a\u4e00\u4e2aNOP\uff0c\u6240\u6709\u82af\u7247\u90fd\u6fc0\u6d3b<\/p>\n<p>@Precharge All<br \/>\nldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_PA0<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_DIRECT_CMD] \u00a0@\u505aprecharge<\/p>\n<p>@Auto Refresh\u00a0\u00a0\u00a0\u00a0 2 time<br \/>\nldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_AR0<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_DIRECT_CMD] \u00a0@\u81ea\u52a8\u5237\u65b0\u4e24\u6b21<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_DIRECT_CMD]<\/p>\n<p>@MRS<br \/>\nldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_mDDR_EMR0<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_DIRECT_CMD] \u00a0@\u505aEMRS<\/p>\n<p>@Mode Reg<br \/>\nldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_mDDR_MR0<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_DIRECT_CMD] \u00a0@\u505aMRS<\/p>\n<p>#ifdef CONFIG_SMDK6410_X5A<br \/>\nldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC1_CHIP1_CFG<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_CHIP_1_CFG]<\/p>\n<p>@DMC0 DDR Chip 0 configuration direct command reg<br \/>\nldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_NOP1<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_DIRECT_CMD]<\/p>\n<p>@Precharge All<br \/>\nldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_PA1<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_DIRECT_CMD]<\/p>\n<p>@Auto Refresh\u00a0\u00a0\u00a0\u00a0 2 time<br \/>\nldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_AR1<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_DIRECT_CMD]<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_DIRECT_CMD]<\/p>\n<p>@MRS<br \/>\nldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_mDDR_EMR1<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_DIRECT_CMD]<\/p>\n<p>@Mode Reg<br \/>\nldr\u00a0\u00a0\u00a0\u00a0 r1, =DMC_mDDR_MR1<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_DIRECT_CMD]<br \/>\n#endif<\/p>\n<p>@Enable DMC1<br \/>\nmov\u00a0\u00a0\u00a0\u00a0 r1, #0x0<br \/>\nstr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_MEMC_CMD] \u00a0 \u00a0 \u00a0 \u00a0@\u8bbe\u7f6eGO\u547d\u4ee4\uff0c\u542f\u7528DMC1<\/p>\n<p>check_dmc1_ready:<br \/>\nldr\u00a0\u00a0\u00a0\u00a0 r1, [r0, #INDEX_DMC_MEMC_STATUS] \u00a0@\u770bSTATUS\u662f\u5426\u4e3a0x01\uff0c\u662f\u5219\u5df2\u7ecfready<br \/>\nmov\u00a0\u00a0\u00a0\u00a0 r2, #0x3<br \/>\nand\u00a0\u00a0\u00a0\u00a0 r1, r1, r2<br \/>\ncmp\u00a0\u00a0\u00a0\u00a0 r1, #0x1<br \/>\nbne\u00a0\u00a0\u00a0\u00a0 check_dmc1_ready<br \/>\nnop<br \/>\nmov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/p>\n<p>\/* Below code is for ARM926EJS and ARM1026EJS *\/<br \/>\n.globl cleanDCache<br \/>\ncleanDCache:<br \/>\nmrc\u00a0\u00a0\u00a0\u00a0 p15, 0, pc, c7, c10, 3\u00a0\u00a0\u00a0\u00a0 \/* test\/clean D-Cache *\/<br \/>\nbne\u00a0\u00a0\u00a0\u00a0 cleanDCache<br \/>\nmov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/p>\n<p>.globl cleanFlushDCache<br \/>\ncleanFlushDCache:<br \/>\nmrc\u00a0\u00a0\u00a0\u00a0 p15, 0, pc, c7, c14, 3\u00a0\u00a0\u00a0\u00a0 \/* test\/cleanflush D-Cache *\/<br \/>\nbne\u00a0\u00a0\u00a0\u00a0 cleanFlushDCache<br \/>\nmov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/p>\n<p>.globl cleanFlushCache<br \/>\ncleanFlushCache:<br \/>\nmrc\u00a0\u00a0\u00a0\u00a0 p15, 0, pc, c7, c14, 3\u00a0\u00a0\u00a0\u00a0 \/* test\/cleanflush D-Cache *\/<br \/>\nbne\u00a0\u00a0\u00a0\u00a0 cleanFlushCache<br \/>\nmcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c5, 0\u00a0\u00a0\u00a0\u00a0 \/* flush I-Cache *\/<br \/>\nmov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/p>\n<p>.ltorg<\/p>\n","protected":false},"excerpt":{"rendered":"<p>#include &lt;config.h&gt; #include &lt;s3c6410.h&gt; .g &hellip;<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[6],"tags":[232,48,49],"class_list":["post-290","post","type-post","status-publish","format-standard","hentry","category-6","tag-cpu_init-s","tag-mini6410","tag-uboot"],"views":1418,"_links":{"self":[{"href":"http:\/\/www.max-shu.com\/blog\/index.php?rest_route=\/wp\/v2\/posts\/290","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.max-shu.com\/blog\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.max-shu.com\/blog\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.max-shu.com\/blog\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.max-shu.com\/blog\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=290"}],"version-history":[{"count":1,"href":"http:\/\/www.max-shu.com\/blog\/index.php?rest_route=\/wp\/v2\/posts\/290\/revisions"}],"predecessor-version":[{"id":291,"href":"http:\/\/www.max-shu.com\/blog\/index.php?rest_route=\/wp\/v2\/posts\/290\/revisions\/291"}],"wp:attachment":[{"href":"http:\/\/www.max-shu.com\/blog\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=290"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.max-shu.com\/blog\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=290"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.max-shu.com\/blog\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=290"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}