{"id":307,"date":"2018-03-13T13:48:41","date_gmt":"2018-03-13T05:48:41","guid":{"rendered":"http:\/\/www.max-shu.com\/blog\/?p=307"},"modified":"2018-03-14T09:33:31","modified_gmt":"2018-03-14T01:33:31","slug":"linux%e7%9a%84arch-arm-kernel-head-s","status":"publish","type":"post","link":"http:\/\/www.max-shu.com\/blog\/?p=307","title":{"rendered":"linux\u7684arch\/arm\/kernel\/head.S"},"content":{"rendered":"<div>#ifdef DEBUG<\/div>\n<div><\/div>\n<div>#if defined(CONFIG_DEBUG_ICEDCC) \u00a0 \u00a0 \u00a0 \u00a0 \/*\u4f7f\u7528ARM EmbeddedICE DCC\u901a\u9053\u6765\u8c03\u8bd5*\/<\/div>\n<div><\/div>\n<div>#ifdef CONFIG_CPU_V6<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .macro\u00a0\u00a0\u00a0\u00a0 loadsp, rb \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u5b9a\u4e49\u4e86\u4e00\u4e2a\u5b8f\uff0c\u5b8f\u540d\u662floadsp\uff0crb\u662f\u8fd9\u4e2a\u5b8f\u7684\u53c2\u6570\u3002\u5b8f\u7684\u53c2\u6570\u5728\u88ab\u5f15\u7528\u65f6\u5fc5\u987b\u52a0\u201d\\\u201d,\u5982\uff1amov \\rb, #0x50000000. *\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .endm<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .macro\u00a0\u00a0\u00a0\u00a0 writeb, ch, rb<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p14, 0, \\ch, c0, c5, 0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*CP14\u8c03\u8bd5\u901a\u4fe1\u901a\u9053\u534f\u5904\u7406\u5668\u8c03\u8bd5\u901a\u4fe1\u901a\u9053\u534f\u5904\u7406\u5668DCC(the Debug Communications Channel)\u63d0\u4f9b\u4e86\u4e24\u4e2a32bits\u5bc4\u5b58\u5668\u7528\u4e8e\u4f20\u9001\u6570\u636e\uff0c\u8fd8\u63d0\u4f9b\u4e866bits\u901a\u4fe1\u6570\u636e\u63a7\u5236\u5bc4\u5b58\u5668\u63a7\u5236\u5bc4\u5b58\u5668\u4e2d\u7684\u4e24\u4e2a\u4f4d\u63d0\u4f9b\u76ee\u6807\u548c\u4e3b\u673a\u8c03\u8bd5\u5668\u4e4b\u95f4\u7684\u540c\u6b65\u63e1\u624b\u3002\u8fd9\u91cc\u628ach\u8fd9\u4e2a\u6570\u636e\u5199\u5165c5\u5bc4\u5b58\u5668\u5bf9\u5e94\u7684ICE\/JTAG\u8c03\u8bd5\u5668\u7684\u5bc4\u5b58\u5668*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .endm<\/div>\n<div>#else<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .macro\u00a0\u00a0\u00a0\u00a0 loadsp, rb<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .endm<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .macro\u00a0\u00a0\u00a0\u00a0 writeb, ch, rb<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p14, 0, \\ch, c1, c0, 0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .endm<\/div>\n<div>#endif<\/div>\n<div><\/div>\n<div>#else<\/div>\n<div><\/div>\n<div>#include &lt;mach\/debug-macro.S&gt;<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .macro\u00a0\u00a0\u00a0\u00a0 writeb,\u00a0\u00a0\u00a0\u00a0 ch, rb<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 senduart \\ch, \\rb \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u628ach\u901a\u8fc7UART\u53d1\u9001\u51fa\u53bb*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .endm<\/div>\n<div><\/div>\n<div>#if defined(CONFIG_ARCH_SA1100)<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .macro\u00a0\u00a0\u00a0\u00a0 loadsp, rb<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 \\rb, #0x80000000\u00a0\u00a0\u00a0\u00a0 @ physical base address<\/div>\n<div>#ifdef CONFIG_DEBUG_LL_SER3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 \\rb, \\rb, #0x00050000\u00a0\u00a0\u00a0\u00a0 @ Ser3 \u00a0 \u00a0 \/*rb\u7ed3\u679c\u4e3a0x80050000*\/<\/div>\n<div>#else<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 \\rb, \\rb, #0x00010000\u00a0\u00a0\u00a0\u00a0 @ Ser1<\/div>\n<div>#endif<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .endm<\/div>\n<div>#elif defined(CONFIG_ARCH_S3C2410)<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .macro loadsp, rb<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 \\rb, #0x50000000<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 \\rb, \\rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT \u00a0 \/*\u5f97\u5230UART\u57fa\u5730\u5740\uff1a0x5004(8)000*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .endm<\/div>\n<div>#else<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .macro\u00a0\u00a0\u00a0\u00a0 loadsp,\u00a0\u00a0\u00a0\u00a0 rb<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 addruart \\rb \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u5f97\u5230UART\u57fa\u5730\u5740*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .endm<\/div>\n<div>#endif<\/div>\n<div>#endif<\/div>\n<div>#endif<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .macro\u00a0\u00a0\u00a0\u00a0 kputc,val<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, \\val<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 putc<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .endm<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .macro\u00a0\u00a0\u00a0\u00a0 kphex,val,len<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, \\val<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r1, #\\len<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 phex<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .endm<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .macro\u00a0\u00a0\u00a0\u00a0 debug_reloc_start \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u8f93\u51fa\u91cd\u5b9a\u4f4d\u7684\u8d77\u59cb\u4fe1\u606f\uff0c\u5305\u62ec\u5904\u7406\u5668id\uff0c\u67b6\u6784id\uff0c\u63a7\u5236\u5bc4\u5b58\u5668\u503c\uff0c\u9700\u89e3\u538b\u5185\u6838(gz\u683c\u5f0f)\u7684\u8d77\u59cb\u5730\u5740\uff0c\u7ed3\u675f\u5730\u5740\uff0c\u5185\u6838\u5b9e\u9645\u6267\u884c\u5730\u5740*\/<\/div>\n<div>#ifdef DEBUG<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 kputc\u00a0\u00a0\u00a0\u00a0 #&#8217;\\n&#8217;<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 kphex\u00a0\u00a0\u00a0\u00a0 r6, 8\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/* processor id *\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 kputc\u00a0\u00a0\u00a0\u00a0 #&#8217;:&#8217;<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 kphex\u00a0\u00a0\u00a0\u00a0 r7, 8\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/* architecture id *\/<\/div>\n<div>#ifdef CONFIG_CPU_CP15<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 kputc\u00a0\u00a0\u00a0\u00a0 #&#8217;:&#8217;<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 kphex\u00a0\u00a0\u00a0\u00a0 r0, 8\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/* control reg *\/<\/div>\n<div>#endif<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 kputc\u00a0\u00a0\u00a0\u00a0 #&#8217;\\n&#8217;<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 kphex\u00a0\u00a0\u00a0\u00a0 r5, 8\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/* decompressed kernel start *\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 kputc\u00a0\u00a0\u00a0\u00a0 #&#8217;-&#8216;<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 kphex\u00a0\u00a0\u00a0\u00a0 r9, 8\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/* decompressed kernel end\u00a0 *\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 kputc\u00a0\u00a0\u00a0\u00a0 #&#8217;&gt;&#8217;<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 kphex\u00a0\u00a0\u00a0\u00a0 r4, 8\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/* kernel execution address *\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 kputc\u00a0\u00a0\u00a0\u00a0 #&#8217;\\n&#8217;<\/div>\n<div>#endif<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .endm<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .macro\u00a0\u00a0\u00a0\u00a0 debug_reloc_end \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u8f93\u51fa\u5185\u6838\u5b9e\u9645\u5c06\u8981\u6267\u884c\u7ed3\u675f\u5730\u5740*\/<\/div>\n<div>#ifdef DEBUG<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 kphex\u00a0\u00a0\u00a0\u00a0 r5, 8\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/* end of kernel *\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 kputc\u00a0\u00a0\u00a0\u00a0 #&#8217;\\n&#8217;<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, r4<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 memdump\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/* dump 256 bytes at start of kernel *\/ \u00a0 \/*\u4ece\u5b9e\u9645\u6267\u884c\u5730\u5740\u5f00\u59cb\uff0c\u5c31\u662f\u5df2\u7ecf\u89e3\u538b\u4e86\u7684\u6267\u884c\u5f00\u59cb\uff0c\u8f93\u51fa256\u5b57\u8282\u5185\u5bb9*\/<\/div>\n<div>#endif<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .endm<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .section &#8220;.start&#8221;, #alloc, #execinstr \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*start\u6bb5\u5f00\u59cb\uff0c\u8be5\u6bb5\u542b\u6709\u5206\u914d\u7684\u6570\u636e\u548c\u53ef\u6267\u884c\u7684\u6307\u4ee4*\/<\/div>\n<div>\/*<\/div>\n<div>* sort out different calling conventions<\/div>\n<div>*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .align<\/div>\n<div>start:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .type\u00a0\u00a0\u00a0\u00a0 start,#function \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\u00a0\/*.type\u6307\u5b9astart\u8fd9\u4e2a\u7b26\u53f7\u662f\u51fd\u6570\u7c7b\u578b*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .rept\u00a0\u00a0\u00a0\u00a0 8<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, r0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u4fdd\u75598\u6761\u7a7a\u6307\u4ee4\uff0c\u8ddf\u4e2d\u65ad\u5411\u91cf\u8868\u4e00\u6837\u5927*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .endr<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 1f \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u8df3\u5230\u4e0b\u9762\u76841\u5904\u6267\u884c*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x016f2818\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ Magic numbers to help the loader<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 start\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ absolute load\/run zImage address<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 _edata\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ zImage end address \u00a0\/*\u5b9a\u4e49\u5728vmlinux.lds.in\u91cc\u9762\uff0c\u6574\u4e2a\u957f\u5ea6\u5305\u542b\u6307\u4ee4\u6bb5\u3001GOT\/PLT\u548cDATA\u6bb5*\/<\/div>\n<div>1:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r7, r1\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ save architecture ID \u00a0 \u00a0 \u00a0\/*\u4eceuboot\u4f20\u5165\u7684\u53c2\u6570:r0: \u56fa\u5b9a0\uff0cr1: \u67b6\u6784id\uff0cr2: \u542f\u52a8\u53c2\u6570*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r8, r2\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ save atags pointer<\/div>\n<div><\/div>\n<div>#ifndef __ARM_ARCH_2__<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/*<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * Booting from Angel &#8211; need to enter SVC mode and disable<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * FIQs\/IRQs (numeric definitions from angel arm.h source).<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * We only do this if we were in user mode on entry.<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 *\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrs\u00a0\u00a0\u00a0\u00a0 r2, cpsr\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ get current mode \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u8bfb\u53d6cpsr\u5e76\u5224\u65ad\u662f\u5426\u5904\u7406\u5668\u5904\u4e8esupervisor\u6a21\u5f0f\u2014\u2014\u4eceu-boot\u8fdb\u5165kernel\uff0c\u7cfb\u7edf\u5df2\u7ecf\u5904\u4e8eSVC32\u6a21\u5f0f\uff1b\u800c\u5229\u7528angel\u8fdb\u5165\u5219\u5904\u4e8euser\u6a21\u5f0f\uff0c\u8fd8\u9700\u8981\u989d\u5916\u4e24\u6761\u6307\u4ee4\u3002\u4e4b\u540e\u662f\u518d\u6b21\u786e\u8ba4\u4e2d\u65ad\u5173\u95ed\uff0c\u5e76\u5b8c\u6210cpsr\u5199\u5165\u3002Angel \u662f ARM \u7684\u8c03\u8bd5\u534f\u8bae,\u73b0\u5728\u7528\u7684 MULTI-ICE \u7528\u7684\u662f RDI \u901a\u8baf\u534f\u8bae, ANGLE \u9700\u8981\u5728\u677f\u5b50\u4e0a\u6709 \u9a7b\u7559\u7a0b\u5e8f,\u7136\u540e\u901a\u8fc7 \u4e32\u53e3\u5c31\u53ef\u4ee5\u8c03\u8bd5\u4e86\u3002\u8fd9\u91cc\u4ecb\u7ecd\u4e00\u4e0b\u534a\u4e3b\u673a\uff1a\u534a\u4e3b\u673a\u662f\u7528\u4e8e ARM \u76ee\u6807\u7684\u4e00\u79cd\u673a\u5236\uff0c\u53ef\u5c06\u6765\u81ea\u5e94\u7528\u7a0b\u5e8f\u4ee3\u7801\u7684\u8f93\u5165\/\u8f93\u51fa\u8bf7\u6c42\u4f20\u9001\u81f3\u8fd0\u884c\u8c03\u8bd5\u5668\u7684\u4e3b\u673a\u3002 \u4f8b\u5982\uff0c\u4f7f\u7528\u6b64\u673a\u5236\u53ef\u4ee5\u542f\u7528 C \u5e93\u4e2d\u7684\u51fd\u6570\uff0c\u5982printf() \u548c scanf()\uff0c\u6765\u4f7f\u7528\u4e3b\u673a\u7684\u5c4f\u5e55\u548c\u952e\u76d8\uff0c\u800c\u4e0d\u662f\u5728\u76ee\u6807\u7cfb\u7edf\u4e0a\u914d\u5907\u5c4f\u5e55\u548c\u952e\u76d8\u3002\u534a\u4e3b\u673a\u662f\u901a\u8fc7\u4e00\u7ec4\u5b9a\u4e49\u597d\u7684\u8f6f\u4ef6\u6307\u4ee4\uff08\u5982 swi\uff09\u6765\u5b9e\u73b0\u7684\uff0c\u8fd9\u4e9b\u6307\u4ee4\u901a\u8fc7\u7a0b\u5e8f\u63a7\u5236\u751f\u6210\u5f02\u5e38\u3002 \u5e94\u7528\u7a0b\u5e8f\u8c03\u7528\u76f8\u5e94\u7684\u534a\u4e3b\u673a\u8c03\u7528\uff0c\u7136\u540e\u8c03\u8bd5\u4ee3\u7406\u5904\u7406\u8be5\u5f02\u5e38\u3002 \u8c03\u8bd5\u4ee3\u7406\u63d0\u4f9b\u4e0e\u4e3b\u673a\u4e4b\u95f4\u7684\u5fc5\u9700\u901a\u4fe1\u3002 *\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 tst\u00a0\u00a0\u00a0\u00a0 r2, #3\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ not user?<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bne\u00a0\u00a0\u00a0\u00a0 not_angel<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0x17\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ angel_SWIreason_EnterSVC<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 swi\u00a0\u00a0\u00a0\u00a0 0x123456\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ angel_SWI_ARM \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*0x17\u662fangel_SWIreason_EnterSVC\u534a\u4e3b\u673a\u64cd\u4f5c\uff0c\u5c06\u5904\u7406\u5668\u8bbe\u7f6e\u4e3a\u8d85\u7ea7\u7528\u6237\u6a21\u5f0f\uff0c\u901a\u8fc7\u8bbe\u7f6e\u65b0 CPSR \u4e2d\u7684\u4e24\u4e2a\u4e2d\u65ad\u63a9\u7801\u4f4d\u6765\u7981\u7528\u6240\u6709\u4e2d\u65ad\u30020x123456\u662farm\u6307\u4ee4\u96c6\u7684\u534a\u4e3b\u673a\u64cd\u4f5c\u7f16\u53f7 *\/<\/div>\n<div>not_angel:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrs\u00a0\u00a0\u00a0\u00a0 r2, cpsr\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ turn off interrupts to<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orr\u00a0\u00a0\u00a0\u00a0 r2, r2, #0xc0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ prevent angel from running<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 msr\u00a0\u00a0\u00a0\u00a0 cpsr_c, r2 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u8fd9\u91cc\u5c06cpsr\u4e2dI\u3001F\u4f4d\u5206\u522b\u7f6e\u201c1\u201d\uff0c\u5173\u95edIRQ\u548cFIQ *\/<\/div>\n<div>#else<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 teqp\u00a0\u00a0\u00a0\u00a0 pc, #0x0c000003\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ turn off interrupts \u00a0 \u00a0\/*\u5e38\u7528 TEQP PC,#(\u65b0\u6a21\u5f0f\u7f16\u53f7) \u6765\u6539\u53d8\u6a21\u5f0f\uff0c\u5c31\u662f\u5b58\u5165CPSR\u7684\u503c\u4e3apc^ 0x0c000003\uff08SVC\u6a21\u5f0f\uff09*\/<\/div>\n<div>#endif<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/*<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * Note that some cache flushing and other stuff may<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * be needed here &#8211; is there an Angel SWI call for this?<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 *\/<\/div>\n<div>\/*\u94fe\u63a5\u5668\u4f1a\u628a\u4e00\u4e9b\u5904\u7406\u5668\u76f8\u5173\u7684\u4ee3\u7801\u94fe\u63a5\u5230\u8fd9\u4e2a\u4f4d\u7f6e\uff0c\u4e5f\u5c31\u662farch\/arm\/boot\/compressed\/head-xxx.S\u6587\u4ef6\u4e2d\u7684\u4ee3\u7801\u3002\u5728\u90a3\u4e2a\u6587\u4ef6\u91cc\u4f1a\u5bf9I\/D cache\u4ee5\u53caMMU\u8fdb\u884c\u4e00\u4e9b\u64cd\u4f5c\uff0c\u4f46\u662f\u90fd\u5e94\u8be5\u5c5e\u4e8estart\u6bb5 *\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/*<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * some architecture specific code can be inserted<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * by the linker here, but it should preserve r7, r8, and r9.<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 *\/<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .text \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*text\u6bb5*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 adr\u00a0\u00a0\u00a0\u00a0 r0, LC0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*LC0\u6807\u7b7e\u5b9a\u4e49\u5728\u4e0b\u9762\uff0c\u8fd9\u91ccr0 = pc + LC0\uff0c\u5373\u8fd0\u884c\u65f6LC0\u7684\u5730\u5740*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldmia\u00a0\u00a0\u00a0\u00a0 r0, {r1, r2, r3, r4, r5, r6, ip, sp} \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u628aLC0\u5904\u5b58\u653e\u7684\u5404\u4e2a\u5730\u5740\u8f7d\u5165r1\u5230sp*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 subs\u00a0\u00a0\u00a0\u00a0 r0, r0, r1\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ calculate the delta offset \u00a0 \u00a0 \u00a0 \u00a0\/*\u56e0\u4e3ar1\u5373\u4e0b\u9762\u7684LC0\u5904\u8fde\u63a5\u65f6\u5b9a\u4e49\u4e86LC0\u7684\u94fe\u63a5\u5730\u5740(.word\u00a0\u00a0\u00a0\u00a0 LC0)\uff0c\u8fd9\u91cc\u770b\u8fd0\u884c\u65f6\u5730\u5740\u8ddf\u94fe\u63a5\u65f6\u5730\u5740\u662f\u5426\u4e00\u81f4\uff0c\u4e0d\u4e00\u81f4\u5219\u8981\u91cd\u5b9a\u4f4d*\/<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ if delta is zero, we are<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 beq\u00a0\u00a0\u00a0\u00a0 not_relocated\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ running at the address we<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ were linked at.<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/*<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * We&#8217;re running at a different address.\u00a0 We need to fix<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * up various pointers:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 *\u00a0\u00a0 r5 &#8211; zImage base address<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 *\u00a0\u00a0 r6 &#8211; GOT start<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 *\u00a0\u00a0 ip &#8211; GOT end<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 *\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r5, r5, r0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u91cd\u5b9a\u4f4d\u65f6\u5148\u4fee\u6b63r5\u5373zImage\u7684\u57fa\u5730\u5740_start\uff0c\u6b64\u65f6r0\u4e3a\u8fd0\u884c\u5730\u5740\u4e0e\u94fe\u63a5\u5730\u5740\u7684\u5dee\u503c*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r6, r6, r0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*r6\u57faGOT\u8d77\u59cb\u5730\u5740_got_start*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 ip, ip, r0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*ip\u5373GOT\u7ed3\u675f\u5730\u5740_got_end*\/<\/div>\n<div><\/div>\n<div>#ifndef CONFIG_ZBOOT_ROM<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/*<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * If we&#8217;re running fully PIC === CONFIG_ZBOOT_ROM = n,<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * we need to fix up pointers into the BSS region.<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 *\u00a0\u00a0 r2 &#8211; BSS start<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 *\u00a0\u00a0 r3 &#8211; BSS end<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 *\u00a0\u00a0 sp &#8211; stack pointer<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 *\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r2, r2, r0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u4fee\u6b63BSS\u8d77\u59cb\u3001\u7ed3\u675f\u5730\u5740\u548c\u6808\u6307\u9488*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r3, r3, r0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 sp, sp, r0<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/*<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * Relocate all entries in the GOT table.<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 *\/<\/div>\n<div>1:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldr\u00a0\u00a0\u00a0\u00a0 r1, [r6, #0]\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ relocate entries in the GOT \/*\u53d6\u5f97r6\u5373GOT\u8868\u7684\u8d77\u59cb\u5730\u5740\u5904\u7684\u503c\u5373\u9875\u8868\u63cf\u8ff0\u7b26*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r1, r1, r0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ table.\u00a0 This fixes up the \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u4fee\u6b63\u63cf\u8ff0\u7b26*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 str\u00a0\u00a0\u00a0\u00a0 r1, [r6], #4\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ C references. \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u5b58\u5165\u9875\u8868\uff0cr6\u6307\u5411\u4e0b\u4e00\u4e2a\u63cf\u8ff0\u7b26*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 cmp\u00a0\u00a0\u00a0\u00a0 r6, ip \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u662f\u5426\u5b8c\u6210\uff0cip\u4e3aGOT\u7ed3\u675f\u5730\u5740*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 blo\u00a0\u00a0\u00a0\u00a0 1b<\/div>\n<div>#else<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/*<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * Relocate entries in the GOT table.\u00a0 We only relocate<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * the entries that are outside the (relocated) BSS region.<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 *\/<\/div>\n<div>1:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldr\u00a0\u00a0\u00a0\u00a0 r1, [r6, #0]\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ relocate entries in the GOT \u00a0 \/*\u5bf9got\u8868\u4e2d\u5728bss\u6bb5\u4ee5\u5916\u7684\u7b26\u53f7\u8fdb\u884c\u91cd\u5b9a\u4f4d\uff0c\u4e00\u7ea7\u63cf\u8ff0\u7b26\u8868\u7684\u9ad812\u4f4d\u662f\u6bcf\u4e2asetcion\u7684\u57fa\u5730\u5740\uff0c\u53ef\u4ee5\u63cf\u8ff04096\u4e2asection\u3002\u4e00\u7ea7\u9875\u8868\u5927\u5c0f\u4e3a16K\uff0c\u6bcf\u4e2a\u9875\u8868\u9879\uff0c\u5373\u63cf\u8ff0\u7b26\u53604\u5b57\u8282\uff0c\u521a\u597d\u53ef\u4ee5\u5bb9\u7eb34096\u4e2a\u63cf\u8ff0\u7b26\uff0c\u6240\u4ee5\u8fd9\u91cc\u5c31\u6620\u5c04\u4e864096*1M = 4G\u7684\u7a7a\u95f4\u3002 *\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 cmp\u00a0\u00a0\u00a0\u00a0 r1, r2\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ entry &lt; bss_start ||<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 cmphs\u00a0\u00a0\u00a0\u00a0 r3, r1\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ _end &lt; entry<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 addlo\u00a0\u00a0\u00a0\u00a0 r1, r1, r0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ table.\u00a0 This fixes up the<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 str\u00a0\u00a0\u00a0\u00a0 r1, [r6], #4\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ C references.<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 cmp\u00a0\u00a0\u00a0\u00a0 r6, ip<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 blo\u00a0\u00a0\u00a0\u00a0 1b<\/div>\n<div>#endif<\/div>\n<div><\/div>\n<div>not_relocated:\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0<\/div>\n<div>1:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 str\u00a0\u00a0\u00a0\u00a0 r0, [r2], #4\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ clear bss \u00a0 \u00a0\/*\u628abss\u6bb5\u6e05\u7a7a*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 str\u00a0\u00a0\u00a0\u00a0 r0, [r2], #4<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 str\u00a0\u00a0\u00a0\u00a0 r0, [r2], #4<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 str\u00a0\u00a0\u00a0\u00a0 r0, [r2], #4<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 cmp\u00a0\u00a0\u00a0\u00a0 r2, r3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 blo\u00a0\u00a0\u00a0\u00a0 1b<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/*<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * The C runtime environment should now be setup<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * sufficiently.\u00a0 Turn the cache on, set up some<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 * pointers, and start decompressing.<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 *\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 cache_on \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u6253\u5f00cache\uff0c\u770b\u4e0b\u9762\u4ee3\u7801*\/<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r1, sp\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ malloc space above stack<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r2, sp, #0x10000\u00a0\u00a0\u00a0\u00a0 @ 64k max \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u6808\u7a7a\u95f4\u5927\u5c0f\u662f4096\u5b57\u8282\uff0c\u90a3\u4e48\u5728\u6808\u7a7a\u95f4\u5730\u5740\u4e0a\u9762\u518dmalloc 64K\u5b57\u8282\u7a7a\u95f4\uff0c\u8fd9\u4e2a\u7ed9c\u51fd\u6570malloc\u3001free\u7528*\/<\/div>\n<div><\/div>\n<div>\/*<\/div>\n<div>* Check to see if we will overwrite ourselves.<\/div>\n<div>*\u00a0\u00a0 r4 = final kernel address \u00a0 \u00a0 \u00a0 \/*\u6700\u7ec8\u89e3\u538b\u540e\u7684\u5185\u6838\u5730\u5740*\/<\/div>\n<div>*\u00a0\u00a0 r5 = start of this image \u00a0 \u00a0 \u00a0 \u00a0 \/*zImage\u7684\u8fd0\u884c\u65f6\u5730\u5740\uff0c\u5c31\u662f\u8fd9\u4e2ahead.S\u7684start\u5904\u7684\u5730\u5740*\/<\/div>\n<div>*\u00a0\u00a0 r2 = end of malloc space (and therefore this image) \/*\u6307\u5411\u6808\u518d\u52a064KB\u5904*\/<\/div>\n<div>* We basically want:<\/div>\n<div>*\u00a0\u00a0 r4 &gt;= r2 -&gt; OK<\/div>\n<div>*\u00a0\u00a0 r4 + image length &lt;= r5 -&gt; OK<\/div>\n<div>*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 cmp\u00a0\u00a0\u00a0\u00a0 r4, r2<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bhs\u00a0\u00a0\u00a0\u00a0 wont_overwrite \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*r4&gt;r2\u5f53\u7136\u5c31\u4e0d\u4f1a\u53d1\u751f\u5730\u5740\u51b2\u7a81*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 sub\u00a0\u00a0\u00a0\u00a0 r3, sp, r5\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ &gt; compressed kernel size<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r0, r4, r3, lsl #2\u00a0\u00a0\u00a0\u00a0 @ allow for 4x expansion<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 cmp\u00a0\u00a0\u00a0\u00a0 r0, r5<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bls\u00a0\u00a0\u00a0\u00a0 wont_overwrite \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*r5 &gt; r4 + zimage\u957f\u5ea6\uff0c\u4e5f\u4e0d\u4f1a\u51b2\u7a81*\/<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r5, r2\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ decompress after malloc space \/*\u6709\u51b2\u7a81\uff0c\u5148\u89e3\u538b\u5230r2\u5f00\u59cb\u7684\u4f4d\u7f6e\uff0c\u7136\u540e\u628a\u5c06\u8981\u88ab\u8986\u76d6\u7684\u4ee3\u7801\u6bb5\u632a\u5230\u89e3\u538b\u4e4b\u540e\u7684vmlinux\u7684\u4e0a\u9762\uff0c\u6700\u540e\u628a\u89e3\u538b\u540e\u7684vmlinux\u632a\u5230\u6267\u884c\u4f4d\u7f6er4\u4f4d\u7f6e*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, r5<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r3, r7<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 decompress_kernel \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*misc.c\u7684\u51fd\u6570\uff0c\u89e3\u538b\u5185\u6838\uff0cr0\uff1a\u89e3\u538b\u540e\u7684\u8d77\u59cb\u5730\u5740\uff0cr1\uff1amalloc\u5185\u5b58\u65f6\u7684\u5f00\u59cb\u4f4d\u7f6e\uff0cr2\uff1amalloc\u5185\u5b58\u65f6\u7684\u7ed3\u675f\u4f4d\u7f6e\uff0cr3\uff1a\u67b6\u6784id\uff1b\u89e3\u538b\u7f29\u7684\u65f6\u5019\u4e0d\u9700\u8981\u538b\u7f29\u6620\u8c61\u7684\u8d77\u59cb\u5730\u5740\uff0c\u56e0\u4e3a\u5728misc.c\u91cc\u9762\u76f4\u63a5\u4f7f\u7528\u7684\u662farh\/arm\/boot\/compressed\/piggy.S\u91cc\u9762\u5b9a\u4e49\u7684input_data\u548cinput_data_end\u3002*\/<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r0, r0, #127 + 128\u00a0\u00a0\u00a0\u00a0 @ alignment + stack<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bic\u00a0\u00a0\u00a0\u00a0 r0, r0, #127\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ align the kernel length \/*r0\u4e3a\u89e3\u538b\u51fd\u6570\u8fd4\u56de\u7684\u89e3\u538b\u7f29\u540e\u7684\u5185\u6838\u5f00\u59cb\u4f4d\u7f6e\uff0c\u8fd9\u91cc\u628a\u5185\u6838\u5bf9\u9f50\u5230128\u5b57\u8282*\/<\/div>\n<div>\/*<\/div>\n<div>* r0\u00a0\u00a0\u00a0\u00a0 = decompressed kernel length<\/div>\n<div>* r1-r3\u00a0 = unused<\/div>\n<div>* r4\u00a0\u00a0\u00a0\u00a0 = kernel execution address<\/div>\n<div>* r5\u00a0\u00a0\u00a0\u00a0 = decompressed kernel start<\/div>\n<div>* r6\u00a0\u00a0\u00a0\u00a0 = processor ID<\/div>\n<div>* r7\u00a0\u00a0\u00a0\u00a0 = architecture ID<\/div>\n<div>* r8\u00a0\u00a0\u00a0\u00a0 = atags pointer<\/div>\n<div>* r9-r14 = corrupted<\/div>\n<div>*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r1, r5, r0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ end of decompressed kernel \u00a0 \/*r1\u4e3a\u89e3\u538b\u7f29\u540e\u7684\u5185\u6838\u7ed3\u675f\u4f4d\u7f6e*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 adr\u00a0\u00a0\u00a0\u00a0 r2, reloc_start \u00a0 \u00a0 \/*\u628a\u540e\u9762\u9700\u8981\u4f7f\u7528\u5230\u7684\u4ee3\u7801\u632a\u5230\u89e3\u538b\u7f29\u540e\u7684\u5185\u6838\u7684\u540e\u9762\u4f4d\u7f6e\uff0creloc_start\u4e3a\u4ee3\u7801\u8d77\u59cb\u4f4d\u7f6e*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldr\u00a0\u00a0\u00a0\u00a0 r3, LC1 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u9700\u8981reloc\u91cd\u5b9a\u4f4d\u7684\u5927\u5c0f*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r3, r2, r3 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*r3\u4e3a\u7ed3\u675f\u5730\u5740*\/<\/div>\n<div>1:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldmia\u00a0\u00a0\u00a0\u00a0 r2!, {r9 &#8211; r14}\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ copy relocation code<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 stmia\u00a0\u00a0\u00a0\u00a0 r1!, {r9 &#8211; r14} \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u642c\u79fb\u4ee3\u7801*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldmia\u00a0\u00a0\u00a0\u00a0 r2!, {r9 &#8211; r14}<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 stmia\u00a0\u00a0\u00a0\u00a0 r1!, {r9 &#8211; r14}<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 cmp\u00a0\u00a0\u00a0\u00a0 r2, r3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 blo\u00a0\u00a0\u00a0\u00a0 1b<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 sp, r1, #128\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ relocate the stack \u00a0\/*\u91cd\u5b9a\u4f4d\u6808\u6307\u9488*\/<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 cache_clean_flush \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*flush\u6240\u6709cache*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 pc, r5, r0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ call relocation code \u00a0\/*\u8df3\u8f6c\u5230reloc_start\u4f4d\u7f6e\u6267\u884c*\/<\/div>\n<div><\/div>\n<div>\/*<\/div>\n<div>* We&#8217;re not in danger of overwriting ourselves.\u00a0 Do this the simple way.<\/div>\n<div>*<\/div>\n<div>* r4\u00a0\u00a0\u00a0\u00a0 = kernel execution address<\/div>\n<div>* r7\u00a0\u00a0\u00a0\u00a0 = architecture ID<\/div>\n<div>*\/<\/div>\n<div>wont_overwrite:\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, r4 \u00a0 \u00a0 \/*\u8bbe\u7f6e\u8d77\u59cb\u5730\u5740*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r3, r7 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u67b6\u6784id*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 decompress_kernel \u00a0 \u00a0 \u00a0\/*\u76f4\u63a5\u89e3\u538b\u7f29*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 call_kernel \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u8c03\u7528call_kernel\uff0c\u7136\u540e\u8fd0\u884c\u771f\u6b63\u7684\u5185\u6838*\/<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .type\u00a0\u00a0\u00a0\u00a0 LC0, #object \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u5bf9\u8c61LC0\u5b58\u653e\u5404\u4e2a\u5165\u53e3\u5730\u5740*\/<\/div>\n<div>LC0:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 LC0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ r1<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 __bss_start\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ r2<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 _end\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ r3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 zreladdr\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ r4 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u8fd9\u4e2a\u5b9a\u4e49\u5728makefile\u6587\u4ef6\u4e2d\uff1aZRELADDR*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 _start\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ r5<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 _got_start\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ r6<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 _got_end\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ ip<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 user_stack+4096\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ sp<\/div>\n<div>LC1:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 reloc_end &#8211; reloc_start \u00a0\/*\u9700\u8981\u91cd\u5b9a\u4f4d\u7684\u957f\u5ea6*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .size\u00a0\u00a0\u00a0\u00a0 LC0, . &#8211; LC0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*LC0\u5927\u5c0f*\/<\/div>\n<div><\/div>\n<div>#ifdef CONFIG_ARCH_RPC<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .globl\u00a0\u00a0\u00a0\u00a0 params<\/div>\n<div>params:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldr\u00a0\u00a0\u00a0\u00a0 r0, =params_phys<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .ltorg<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .align<\/div>\n<div>#endif<\/div>\n<div><\/div>\n<div>\/*<\/div>\n<div>* Turn on the cache.\u00a0 We need to setup some page tables so that we<\/div>\n<div>* can have both the I and D caches on.<\/div>\n<div>*<\/div>\n<div>* We place the page tables 16k down from the kernel execution address,<\/div>\n<div>* and we hope that nothing else is using it.\u00a0 If we&#8217;re using it, we<\/div>\n<div>* will go pop!<\/div>\n<div>*<\/div>\n<div>* On entry,<\/div>\n<div>*\u00a0 r4 = kernel execution address<\/div>\n<div>*\u00a0 r6 = processor ID<\/div>\n<div>*\u00a0 r7 = architecture number<\/div>\n<div>*\u00a0 r8 = atags pointer<\/div>\n<div>*\u00a0 r9 = run-time address of &#8220;start&#8221;\u00a0 (???)<\/div>\n<div>* On exit,<\/div>\n<div>*\u00a0 r1, r2, r3, r9, r10, r12 corrupted<\/div>\n<div>* This routine must preserve:<\/div>\n<div>*\u00a0 r4, r5, r6, r7, r8<\/div>\n<div>*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .align\u00a0\u00a0\u00a0\u00a0 5 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*2^5=32\uff0c\u53734\u5b57\u8282\u5bf9\u9f50*\/<\/div>\n<div>cache_on:\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r3, #8\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ cache_on function \u00a0 \/*r3\u4e3a\u504f\u79fb\u91cf\uff0c\u8fd9\u91cc\u4e3a8\uff0c\u5c31\u662fcache_on\uff0c\u5982\u679c\u4e3a12\uff0c\u5c31\u662fcache_off*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 call_cache_fn \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u8c03\u7528cache\u51fd\u6570*\/<\/div>\n<div><\/div>\n<div>\/*<\/div>\n<div>* Initialize the highest priority protection region, PR7<\/div>\n<div>* to cover all 32bit address and cacheable and bufferable.<\/div>\n<div>*\/<\/div>\n<div>__armv4_mpu_cache_on:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0x3f\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ 4G, the whole<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c6, c7, 0\u00a0\u00a0\u00a0\u00a0 @ PR7 Area Setting<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr \u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c6, c7, 1<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0x80\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ PR7<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c2, c0, 0\u00a0\u00a0\u00a0\u00a0 @ D-cache on<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c2, c0, 1\u00a0\u00a0\u00a0\u00a0 @ I-cache on<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c3, c0, 0\u00a0\u00a0\u00a0\u00a0 @ write-buffer on<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0xc000<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c5, c0, 1\u00a0\u00a0\u00a0\u00a0 @ I-access permission<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c5, c0, 0\u00a0\u00a0\u00a0\u00a0 @ D-access permission<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c10, 4\u00a0\u00a0\u00a0\u00a0 @ drain write buffer<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c5, 0\u00a0\u00a0\u00a0\u00a0 @ flush(inval) I-Cache<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c6, 0\u00a0\u00a0\u00a0\u00a0 @ flush(inval) D-Cache<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 0\u00a0\u00a0\u00a0\u00a0 @ read control reg<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ &#8230;I &#8230;. ..D. WC.M<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orr\u00a0\u00a0\u00a0\u00a0 r0, r0, #0x002d\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ &#8230;. &#8230;. ..1. 11.1<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orr\u00a0\u00a0\u00a0\u00a0 r0, r0, #0x1000\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ &#8230;1 &#8230;. &#8230;. &#8230;.<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 0\u00a0\u00a0\u00a0\u00a0 @ write control reg<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c5, 0\u00a0\u00a0\u00a0\u00a0 @ flush(inval) I-Cache<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c6, 0\u00a0\u00a0\u00a0\u00a0 @ flush(inval) D-Cache<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div>__armv3_mpu_cache_on:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0x3f\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ 4G, the whole<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c6, c7, 0\u00a0\u00a0\u00a0\u00a0 @ PR7 Area Setting<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0x80\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ PR7<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c2, c0, 0\u00a0\u00a0\u00a0\u00a0 @ cache on<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c3, c0, 0\u00a0\u00a0\u00a0\u00a0 @ write-buffer on<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0xc000<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c5, c0, 0\u00a0\u00a0\u00a0\u00a0 @ access permission<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c0, 0\u00a0\u00a0\u00a0\u00a0 @ invalidate whole cache v3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 0\u00a0\u00a0\u00a0\u00a0 @ read control reg<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ &#8230;. &#8230;. &#8230;. WC.M<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orr\u00a0\u00a0\u00a0\u00a0 r0, r0, #0x000d\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ &#8230;. &#8230;. &#8230;. 11.1<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 0\u00a0\u00a0\u00a0\u00a0 @ write control reg<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c0, 0\u00a0\u00a0\u00a0\u00a0 @ invalidate whole cache v3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div>__setup_mmu:\u00a0\u00a0\u00a0\u00a0 sub\u00a0\u00a0\u00a0\u00a0 r3, r4, #16384\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ Page directory size \u00a0\/*\u8fd9\u91ccr4\u4e2d\u5b58\u653e\u7740\u5185\u6838\u6267\u884c\u5730\u5740\uff0c\u5c0616K\u7684\u4e00\u7ea7\u9875\u8868\u653e\u5728\u8fd9\u4e2a\u5185\u6838\u6267\u884c\u5730\u5740\u4e0b\u9762\u768416K\u7a7a\u95f4\u91cc\uff0c\u4e0a\u9762\u901a\u8fc7 sub\u00a0 r3, r4, #16384\u00a0 \u83b7\u5f9716K\u7a7a\u95f4\u540e\uff0c\u53c8\u5c06\u9875\u8868\u7684\u8d77\u59cb\u5730\u5740\u8fdb\u884c16K\u5bf9\u9f50\u653e\u5728r3\u4e2d\u3002\u5373ttb\u7684\u4f4e14\u4f4d\u6e05\u96f6\u3002*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bic\u00a0\u00a0\u00a0\u00a0 r3, r3, #0xff\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ Align the pointer<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bic\u00a0\u00a0\u00a0\u00a0 r3, r3, #0x3f00<\/div>\n<div>\/*<\/div>\n<div>* Initialise the page tables, turning on the cacheable and bufferable<\/div>\n<div>* bits for the RAM area only.<\/div>\n<div>*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, r3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r9, r0, lsr #18<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r9, r9, lsl #18\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ start of RAM<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r10, r9, #0x10000000\u00a0\u00a0\u00a0\u00a0 @ a reasonable RAM size \u00a0\/*\u628a\u4e00\u7ea7\u9875\u8868\u7684\u8d77\u59cb\u5730\u5740\u4fdd\u5b58\u5728r0\u4e2d\uff0c\u5e76\u901a\u8fc7r0\u83b7\u5f97\u4e00\u4e2aram\u8d77\u59cb\u5730\u5740\uff08\u6bcf\u4e2a\u9875\u9762\u5927\u5c0f\u4e3a1M\uff09\u7136\u540e\u6620\u5c04256M ram\u7a7a\u95f4*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r1, #0x12 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u4e00\u7ea7\u63cf\u8ff0\u7b26\u7684bit[1:0]\u4e3a10\uff0c\u8868\u793a\u8fd9\u662f\u4e00\u4e2asection\u63cf\u8ff0\u7b26\u3002\u4e5f\u5373\u5206\u9875\u65b9\u5f0f\u4e3a\u6bb5\u5f0f\u5206\u9875*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orr\u00a0\u00a0\u00a0\u00a0 r1, r1, #3 &lt;&lt; 10 \u00a0 \u00a0 \/*\u4e00\u7ea7\u63cf\u8ff0\u7b26\u7684access permission bits bit[11:10]\u4e3a11*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r2, r3, #16384 \u00a0 \u00a0 \u00a0 \/*\u4e00\u7ea7\u63cf\u8ff0\u7b26\u8868\u7684\u7ed3\u675f\u5730\u5740\u5b58\u653e\u5728r2\u4e2d*\/<\/div>\n<div>1:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 cmp\u00a0\u00a0\u00a0\u00a0 r1, r9\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ if virt &gt; start of RAM \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u865a\u62df\u5730\u5740\u5927\u4e8eRAM\u7684\u8d77\u59cb\u5730\u5740*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orrhs\u00a0\u00a0\u00a0\u00a0 r1, r1, #0x0c\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ set cacheable, bufferable \u00a0 \/*\u521d\u59cb\u5316\u9875\u8868\uff0c\u5e76\u5728RAM\u7a7a\u95f4\u91cc\u6253\u5f00cacheable \u548cbufferable\u4f4d*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 cmp\u00a0\u00a0\u00a0\u00a0 r1, r10\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ if virt &gt; end of RAM \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u865a\u62df\u5730\u5740\u5927\u4e8eRAM\u7684\u7ed3\u675f\u5730\u5740*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bichs\u00a0\u00a0\u00a0\u00a0 r1, r1, #0x0c\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ clear cacheable, bufferable \/*\u6e05\u9664cacheable\u548cbufferable\u4f4d*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 str\u00a0\u00a0\u00a0\u00a0 r1, [r0], #4\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ 1:1 mapping \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u4fdd\u5b58\u6620\u5c04*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r1, r1, #1048576 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u5904\u7406\u4e0b1MB*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 teq\u00a0\u00a0\u00a0\u00a0 r0, r2 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u76f4\u5230\u7ed3\u675f*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bne\u00a0\u00a0\u00a0\u00a0 1b<\/div>\n<div>\/*<\/div>\n<div>* If ever we are running from Flash, then we surely want the cache<\/div>\n<div>* to be enabled also for our execution instance&#8230;\u00a0 We map 2MB of it<\/div>\n<div>* so there is no map overlap problem for up to 1 MB compressed kernel.<\/div>\n<div>* If the execution is in RAM then we would only be duplicating the above.<\/div>\n<div>*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r1, #0x1e<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orr\u00a0\u00a0\u00a0\u00a0 r1, r1, #3 &lt;&lt; 10 \u00a0 \u00a0 \/*\u8fd9\u4e24\u884c\u5c06\u63cf\u8ff0\u7684bit[11:10] bit[4:1]\u7f6e\u4f4d*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r2, pc, lsr #20<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orr\u00a0\u00a0\u00a0\u00a0 r1, r1, r2, lsl #20 \u00a0 \u00a0\/*\u5c06\u5f53\u524d\u5730\u5740\u8fdb1M\u5bf9\u9f50\uff0c\u5e76\u4e0er1\u4e2d\u7684\u5185\u5bb9\u7ed3\u5408\u5f62\u6210\u4e00\u4e2a\u63cf\u8ff0\u5f53\u524d\u6307\u4ee4\u6240\u5728section\u7684\u63cf\u8ff0\u7b26*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r0, r3, r2, lsl #2 \u00a0 \u00a0 \/*r3\u4e3a\u521a\u624d\u5efa\u7acb\u7684\u4e00\u7ea7\u63cf\u8ff0\u7b26\u8868\u7684\u8d77\u59cb\u5730\u5740\u3002\u901a\u8fc7\u5c06\u5f53\u524d\u5730\u5740(pc)\u7684\u9ad812\u4f4d\u5de6\u79fb\u4e24\u4f4d(\u5f62\u621014\u4f4d\u7d22\u5f15)\u4e0er3\u4e2d\u7684\u5730\u5740 (\u4f4e14\u4f4d\u4e3a0)\u76f8\u52a0\u5f62\u6210\u4e00\u4e2a4\u5b57\u8282\u5bf9\u9f50\u7684\u5730\u5740\uff0c\u8fd9\u4e2a\u5730\u5740\u4e5f\u572816K\u7684\u4e00\u7ea7\u63cf\u8ff0\u7b26\u8868\u5185\u3002\u5f53\u524d\u5730\u5740\u5bf9\u5e94\u7684\u63cf\u8ff0\u7b26\u5728\u4e00\u7ea7\u9875\u8868\u4e2d\u7684\u4f4d\u7f6e*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 str\u00a0\u00a0\u00a0\u00a0 r1, [r0], #4<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r1, r1, #1048576<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 str\u00a0\u00a0\u00a0\u00a0 r1, [r0] \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u8fd9\u91cc\u5c06\u4e0a\u9762\u5f62\u6210\u7684\u63cf\u8ff0\u7b26\u53ca\u5176\u8fde\u7eed\u7684\u4e0b\u4e00\u4e2asection\u63cf\u8ff0\u5199\u5165\u4e0a\u97624\u5b57\u8282\u5bf9\u9f50\u5730\u5740\u5904\uff08\u4e00\u7ea7\u9875\u8868\u4e2d\u7d22\u5f15\u4e3ar2\u5de6\u79fb2\u4f4d\uff09*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div>ENDPROC(__setup_mmu)<\/div>\n<div><\/div>\n<div>__armv4_mmu_cache_on:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r12, lr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 __setup_mmu \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u89c1\u4e0a\u9762__setup_mmu\u51fd\u6570*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c10, 4\u00a0\u00a0\u00a0\u00a0 @ drain write buffer \u00a0\/*\u6e05\u7a7a\u5199\u7f13\u51b2\u533a\uff0cI\/D tlb\uff0c\u8bbe\u7f6er0\u4e3aI cache\u4f7f\u80fd\uff0cRR cache\u53ef\u66ff\u6362*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c8, c7, 0\u00a0\u00a0\u00a0\u00a0 @ flush I,D TLBs<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 0\u00a0\u00a0\u00a0\u00a0 @ read control reg<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orr\u00a0\u00a0\u00a0\u00a0 r0, r0, #0x5000\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ I-cache enable, RR cache replacement<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orr\u00a0\u00a0\u00a0\u00a0 r0, r0, #0x0030<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 __common_mmu_cache_on \u00a0 \/*\u8c03\u7528\u4e0b\u9762\u7684__common_mmu_cache_on*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c8, c7, 0\u00a0\u00a0\u00a0\u00a0 @ flush I,D TLBs \/*\u6e05\u7a7aI\/DTLB*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, r12 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u8fd4\u56de*\/<\/div>\n<div><\/div>\n<div>__armv7_mmu_cache_on:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r12, lr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r11, c0, c1, 4\u00a0\u00a0\u00a0\u00a0 @ read ID_MMFR0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 tst\u00a0\u00a0\u00a0\u00a0 r11, #0xf\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ VMSA<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 blne\u00a0\u00a0\u00a0\u00a0 __setup_mmu<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c10, 4\u00a0\u00a0\u00a0\u00a0 @ drain write buffer<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 tst\u00a0\u00a0\u00a0\u00a0 r11, #0xf\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ VMSA<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcrne\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c8, c7, 0\u00a0\u00a0\u00a0\u00a0 @ flush I,D TLBs<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 0\u00a0\u00a0\u00a0\u00a0 @ read control reg<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orr\u00a0\u00a0\u00a0\u00a0 r0, r0, #0x5000\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ I-cache enable, RR cache replacement<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orr\u00a0\u00a0\u00a0\u00a0 r0, r0, #0x003c\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ write buffer<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orrne\u00a0\u00a0\u00a0\u00a0 r0, r0, #1\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ MMU enabled<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 movne\u00a0\u00a0\u00a0\u00a0 r1, #-1<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcrne\u00a0\u00a0\u00a0\u00a0 p15, 0, r3, c2, c0, 0\u00a0\u00a0\u00a0\u00a0 @ load page table pointer<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcrne\u00a0\u00a0\u00a0\u00a0 p15, 0, r1, c3, c0, 0\u00a0\u00a0\u00a0\u00a0 @ load domain access control<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 0\u00a0\u00a0\u00a0\u00a0 @ load control register<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 0\u00a0\u00a0\u00a0\u00a0 @ and read it back<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c5, 4\u00a0\u00a0\u00a0\u00a0 @ ISB<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, r12<\/div>\n<div><\/div>\n<div>__arm6_mmu_cache_on:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r12, lr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 __setup_mmu<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c0, 0\u00a0\u00a0\u00a0\u00a0 @ invalidate whole cache v3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c5, c0, 0\u00a0\u00a0\u00a0\u00a0 @ invalidate whole TLB v3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0x30<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 __common_mmu_cache_on<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c5, c0, 0\u00a0\u00a0\u00a0\u00a0 @ invalidate whole TLB v3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, r12<\/div>\n<div><\/div>\n<div>__common_mmu_cache_on: \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u6253\u5f00cache*\/<\/div>\n<div>#ifndef DEBUG<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orr\u00a0\u00a0\u00a0\u00a0 r0, r0, #0x000d\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ Write buffer, mmu<\/div>\n<div>#endif<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r1, #-1<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r3, c2, c0, 0\u00a0\u00a0\u00a0\u00a0 @ load page table pointer \u00a0 \u00a0 \u00a0 \/*\u628a\u9875\u8868\u5730\u5740\u5b58\u4e8e\u534f\u5904\u7406\u5668\u5bc4\u5b58\u5668\u4e2d*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r1, c3, c0, 0\u00a0\u00a0\u00a0\u00a0 @ load domain access control \/*\u8bbe\u7f6edomain access control\u5bc4\u5b58 \u5668*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 1f<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .align\u00a0\u00a0\u00a0\u00a0 5\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ cache line aligned \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*4\u5b57\u8282\u5bf9\u9f50*\/<\/div>\n<div>1:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 0\u00a0\u00a0\u00a0\u00a0 @ load control register \u00a0 \u00a0 \u00a0 \/*\u8f7d\u5165\u63a7\u5236\u5bc4\u5b58\u5668*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 0\u00a0\u00a0\u00a0\u00a0 @ and read it back to \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u8bfb\u56de\u6765*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 sub\u00a0\u00a0\u00a0\u00a0 pc, lr, r0, lsr #32\u00a0\u00a0\u00a0\u00a0 @ properly flush pipeline \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u6e05\u7a7a\u7ba1\u9053\uff0c\u8fd4\u56de*\/<\/div>\n<div><\/div>\n<div>\/*<\/div>\n<div>* All code following this line is relocatable.\u00a0 It is relocated by<\/div>\n<div>* the above code to the end of the decompressed kernel image and<\/div>\n<div>* executed there.\u00a0 During this time, we have no stacks.<\/div>\n<div>*<\/div>\n<div>* r0\u00a0\u00a0\u00a0\u00a0 = decompressed kernel length<\/div>\n<div>* r1-r3\u00a0 = unused<\/div>\n<div>* r4\u00a0\u00a0\u00a0\u00a0 = kernel execution address<\/div>\n<div>* r5\u00a0\u00a0\u00a0\u00a0 = decompressed kernel start<\/div>\n<div>* r6\u00a0\u00a0\u00a0\u00a0 = processor ID<\/div>\n<div>* r7\u00a0\u00a0\u00a0\u00a0 = architecture ID<\/div>\n<div>* r8\u00a0\u00a0\u00a0\u00a0 = atags pointer<\/div>\n<div>* r9-r14 = corrupted<\/div>\n<div>*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .align\u00a0\u00a0\u00a0\u00a0 5<\/div>\n<div>reloc_start:\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r9, r5, r0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 sub\u00a0\u00a0\u00a0\u00a0 r9, r9, #128\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ do not copy the stack \u00a0#r9\u4e3a\u6700\u7ec8vmlinux\u9700\u8981\u653e\u7f6e\u7684\u7ed3\u675f\u4f4d\u7f6e<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 debug_reloc_start<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r1, r4 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*r1\u4e3a\u6700\u7ec8vmliunx\u9700\u8981\u653e\u7f6e\u7684\u5f00\u59cb\u4f4d\u7f6e*\/<\/div>\n<div>1:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .rept\u00a0\u00a0\u00a0\u00a0 4<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldmia\u00a0\u00a0\u00a0\u00a0 r5!, {r0, r2, r3, r10 &#8211; r14}\u00a0\u00a0\u00a0\u00a0 @ relocate kernel \/*\u632a\u52a8\u4ee3\u7801*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 stmia\u00a0\u00a0\u00a0\u00a0 r1!, {r0, r2, r3, r10 &#8211; r14}<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .endr<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 cmp\u00a0\u00a0\u00a0\u00a0 r5, r9<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 blo\u00a0\u00a0\u00a0\u00a0 1b<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 sp, r1, #128\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ relocate the stack \u00a0\/*\u91cd\u65b0\u5b9a\u4f4d\u6808\u6307\u9488*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 debug_reloc_end<\/div>\n<div><\/div>\n<div>call_kernel:\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 cache_clean_flush \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*flush\u6389cache*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 cache_off \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u5173\u6389cache*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ must be zero<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r1, r7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ restore architecture number<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r2, r8\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ restore atags pointer<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, r4\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ call kernel \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u8df3\u8f6c\u5230r4\u5373\u771f\u6b63\u5185\u6838\u7684\u8d77\u59cb\u4f4d\u7f6e\uff0c\u53c2\u6570\uff1ar0: \u56fa\u5b9a0\uff0cr1\uff1a\u67b6\u6784id\uff0cr2\uff1a\u542f\u52a8\u53c2\u6570*\/<\/div>\n<div><\/div>\n<div>\/*<\/div>\n<div>* Here follow the relocatable cache support functions for the<\/div>\n<div>* various processors.\u00a0 This is a generic hook for locating an<\/div>\n<div>* entry and jumping to an instruction at the specified offset<\/div>\n<div>* from the start of the block.\u00a0 Please note this is all position<\/div>\n<div>* independent code.<\/div>\n<div>*<\/div>\n<div>*\u00a0 r1\u00a0 = corrupted<\/div>\n<div>*\u00a0 r2\u00a0 = corrupted<\/div>\n<div>*\u00a0 r3\u00a0 = block offset<\/div>\n<div>*\u00a0 r6\u00a0 = corrupted<\/div>\n<div>*\u00a0 r12 = corrupted<\/div>\n<div>*\/<\/div>\n<div><\/div>\n<div>call_cache_fn:\u00a0\u00a0\u00a0\u00a0 adr\u00a0\u00a0\u00a0\u00a0 r12, proc_types \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u5f97\u5230\u51fd\u6570\u7ed3\u6784\u6570\u7ec4\u5165\u53e3\uff0cproc_types\u5b9a\u4e49\u5728\u4e0b\u9762*\/<\/div>\n<div>#ifdef CONFIG_CPU_CP15<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r6, c0, c0\u00a0\u00a0\u00a0\u00a0 @ get processor ID<\/div>\n<div>#else<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldr\u00a0\u00a0\u00a0\u00a0 r6, =CONFIG_PROCESSOR_ID \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*r6\u4e3a\u5904\u7406\u673aID*\/<\/div>\n<div>#endif<\/div>\n<div>1:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldr\u00a0\u00a0\u00a0\u00a0 r1, [r12, #0]\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ get value \u00a0 \u00a0 \u00a0 \u00a0 \/*\u8fd9\u662f\u4e00\u4e2a\u7ed3\u6784\u6570\u7ec4\uff0c\u7ed3\u6784\u7684\u7b2c\u4e00\u4e2a\u6210\u5458\u4e3a\u67b6\u6784id\uff0c\u7b2c\u4e8c\u4e2a\u6210\u5458\u4e3a\u63a9\u7801\uff0c\u7b2c\u4e09\u4e2a\u6210\u5458\u4e3acache_on\u51fd\u6570\uff0c\u7b2c\u56db\u4e2a\u6210\u5458\u4e3acache_off\u51fd\u6570\uff0c\u7b2c\u4e94\u4e2a\u6210\u5458\u4e3acache_flush\u51fd\u6570\u3002*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldr\u00a0\u00a0\u00a0\u00a0 r2, [r12, #4]\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ get mask<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 eor\u00a0\u00a0\u00a0\u00a0 r1, r1, r6\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ (real ^ match)<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 tst\u00a0\u00a0\u00a0\u00a0 r1, r2\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 &amp; mask<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 addeq\u00a0\u00a0\u00a0\u00a0 pc, r12, r3\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ call cache function \u00a0\/*\u627e\u5230\u5bf9\u5e94\u7684\u7ed3\u6784\u4e86\uff0c\u5219\u8c03\u7528\u7531r3\u51b3\u5b9a\u7684\u54ea\u4e2a\u51fd\u6570\uff0c\u6bd4\u5982r3\u4e3a8\u4e3a\u8c03\u7528cache_on\u51fd\u6570\uff0c\u8fd9\u91cc\u7528pc\u589e\u52a0\u65b9\u5f0f\u8c03\u7528\uff0c\u6240\u4ee5cache_on\u51fd\u6570\u91cc\u8fd4\u56de\u5c31\u610f\u5473\u7740\u4ece\u8fd9\u91cc\u8fd4\u56de\u3002*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r12, r12, #4*5 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*r12\u589e\u52a0\u5230\u4e0b\u4e2a\u7ed3\u6784*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 1b<\/div>\n<div><\/div>\n<div>\/*<\/div>\n<div>* Table for cache operations.\u00a0 This is basically:<\/div>\n<div>*\u00a0\u00a0 &#8211; CPU ID match<\/div>\n<div>*\u00a0\u00a0 &#8211; CPU ID mask<\/div>\n<div>*\u00a0\u00a0 &#8211; &#8216;cache on&#8217; method instruction<\/div>\n<div>*\u00a0\u00a0 &#8211; &#8216;cache off&#8217; method instruction<\/div>\n<div>*\u00a0\u00a0 &#8211; &#8216;cache flush&#8217; method instruction<\/div>\n<div>*<\/div>\n<div>* We match an entry using: ((real_id ^ match) &amp; mask) == 0<\/div>\n<div>*<\/div>\n<div>* Writethrough caches generally only need &#8216;on&#8217; and &#8216;off&#8217;<\/div>\n<div>* methods.\u00a0 Writeback caches _must_ have the flush method<\/div>\n<div>* defined.<\/div>\n<div>*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .type\u00a0\u00a0\u00a0\u00a0 proc_types,#object \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u7ed3\u6784\u8868\uff0c\u6bcf\u4e2a\u7ed3\u678420\u4e2a\u5b57\u8282*\/<\/div>\n<div>proc_types:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x41560600\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ ARM6\/610<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0xffffffe0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __arm6_mmu_cache_off\u00a0\u00a0\u00a0\u00a0 @ works, but slow<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __arm6_mmu_cache_off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div>@\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __arm6_mmu_cache_on\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ untested<\/div>\n<div>@\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __arm6_mmu_cache_off<\/div>\n<div>@\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv3_mmu_cache_flush<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x00000000\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ old ARM ID<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x0000f000<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x41007000\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ ARM7\/710<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0xfff8fe00<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __arm7_mmu_cache_off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __arm7_mmu_cache_off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x41807200\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ ARM720T (writethrough)<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0xffffff00<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_on<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x41007400\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ ARM74x<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0xff00ff00<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv3_mpu_cache_on<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv3_mpu_cache_off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv3_mpu_cache_flush<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x41009400\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ ARM94x<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0xff00ff00<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mpu_cache_on<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mpu_cache_off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mpu_cache_flush<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x00007000\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ ARM7 IDs<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x0000f000<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ Everything from here on will be the new ID system.<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x4401a100\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ sa110 \/ sa1100<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0xffffffe0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_on<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_flush<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x6901b110\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ sa1110<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0xfffffff0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_on<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_flush<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x56050000\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ Feroceon<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0xff0f0000<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_on<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv5tej_mmu_cache_flush<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ These match on the architecture ID<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x00020000\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ ARMv4T<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x000f0000<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_on<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_flush<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x00050000\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ ARMv5TE<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x000f0000<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_on<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_flush<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x00060000\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ ARMv5TEJ<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x000f0000<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_on<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv5tej_mmu_cache_flush<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x0007b000\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ ARMv6<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x000ff000<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_on<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv4_mmu_cache_off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv6_mmu_cache_flush<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x000f0000\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ new CPU Id<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0x000f0000<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv7_mmu_cache_on<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv7_mmu_cache_off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv7_mmu_cache_flush<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ unrecognised type<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .word\u00a0\u00a0\u00a0\u00a0 0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .size\u00a0\u00a0\u00a0\u00a0 proc_types, . &#8211; proc_types \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u7ed3\u6784\u5927\u5c0f*\/<\/div>\n<div><\/div>\n<div>\/*<\/div>\n<div>* Turn off the Cache and MMU.\u00a0 ARMv3 does not support<\/div>\n<div>* reading the control register, but ARMv4 does.<\/div>\n<div>*<\/div>\n<div>* On entry,\u00a0 r6 = processor ID<\/div>\n<div>* On exit,\u00a0\u00a0 r0, r1, r2, r3, r12 corrupted<\/div>\n<div>* This routine must preserve: r4, r6, r7<\/div>\n<div>*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .align\u00a0\u00a0\u00a0\u00a0 5<\/div>\n<div>cache_off:\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r3, #12\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ cache_off function<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 call_cache_fn<\/div>\n<div><\/div>\n<div>__armv4_mpu_cache_off:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bic\u00a0\u00a0\u00a0\u00a0 r0, r0, #0x000d<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0\u00a0\u00a0\u00a0\u00a0 @ turn MPU and cache off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c10, 4\u00a0\u00a0\u00a0\u00a0 @ drain write buffer<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c6, 0\u00a0\u00a0\u00a0\u00a0 @ flush D-Cache<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c5, 0\u00a0\u00a0\u00a0\u00a0 @ flush I-Cache<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div>__armv3_mpu_cache_off:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bic\u00a0\u00a0\u00a0\u00a0 r0, r0, #0x000d<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 0\u00a0\u00a0\u00a0\u00a0 @ turn MPU and cache off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c0, 0\u00a0\u00a0\u00a0\u00a0 @ invalidate whole cache v3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div>__armv4_mmu_cache_off:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bic\u00a0\u00a0\u00a0\u00a0 r0, r0, #0x000d<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0\u00a0\u00a0\u00a0\u00a0 @ turn MMU and cache off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c7\u00a0\u00a0\u00a0\u00a0 @ invalidate whole cache v4<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c8, c7\u00a0\u00a0\u00a0\u00a0 @ invalidate whole TLB v4<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div>__armv7_mmu_cache_off:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bic\u00a0\u00a0\u00a0\u00a0 r0, r0, #0x000d<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0\u00a0\u00a0\u00a0\u00a0 @ turn MMU and cache off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r12, lr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 __armv7_mmu_cache_flush<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c8, c7, 0\u00a0\u00a0\u00a0\u00a0 @ invalidate whole TLB<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, r12<\/div>\n<div><\/div>\n<div>__arm6_mmu_cache_off:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0x00000030\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ ARM6 control reg.<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv3_mmu_cache_off<\/div>\n<div><\/div>\n<div>__arm7_mmu_cache_off:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0x00000070\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ ARM7 control reg.<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 __armv3_mmu_cache_off<\/div>\n<div><\/div>\n<div>__armv3_mmu_cache_off:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 0\u00a0\u00a0\u00a0\u00a0 @ turn MMU and cache off<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c0, 0\u00a0\u00a0\u00a0\u00a0 @ invalidate whole cache v3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c5, c0, 0\u00a0\u00a0\u00a0\u00a0 @ invalidate whole TLB v3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div>\/*<\/div>\n<div>* Clean and flush the cache to maintain consistency.<\/div>\n<div>*<\/div>\n<div>* On entry,<\/div>\n<div>*\u00a0 r6 = processor ID<\/div>\n<div>* On exit,<\/div>\n<div>*\u00a0 r1, r2, r3, r11, r12 corrupted<\/div>\n<div>* This routine must preserve:<\/div>\n<div>*\u00a0 r0, r4, r5, r6, r7<\/div>\n<div>*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .align\u00a0\u00a0\u00a0\u00a0 5<\/div>\n<div>cache_clean_flush:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r3, #16<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 call_cache_fn<\/div>\n<div><\/div>\n<div>__armv4_mpu_cache_flush:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r2, #1<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r3, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, ip, c7, c6, 0\u00a0\u00a0\u00a0\u00a0 @ invalidate D cache<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r1, #7 &lt;&lt; 5\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ 8 segments<\/div>\n<div>1:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orr\u00a0\u00a0\u00a0\u00a0 r3, r1, #63 &lt;&lt; 26\u00a0\u00a0\u00a0\u00a0 @ 64 entries<\/div>\n<div>2:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r3, c7, c14, 2\u00a0\u00a0\u00a0\u00a0 @ clean &amp; invalidate D index<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 subs\u00a0\u00a0\u00a0\u00a0 r3, r3, #1 &lt;&lt; 26<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bcs\u00a0\u00a0\u00a0\u00a0 2b\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ entries 63 to 0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 subs \u00a0\u00a0\u00a0\u00a0 r1, r1, #1 &lt;&lt; 5<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bcs\u00a0\u00a0\u00a0\u00a0 1b\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ segments 7 to 0<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 teq\u00a0\u00a0\u00a0\u00a0 r2, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcrne\u00a0\u00a0\u00a0\u00a0 p15, 0, ip, c7, c5, 0\u00a0\u00a0\u00a0\u00a0 @ invalidate I cache<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, ip, c7, c10, 4\u00a0\u00a0\u00a0\u00a0 @ drain WB<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div><\/div>\n<div>__armv6_mmu_cache_flush:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r1, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r1, c7, c14, 0\u00a0\u00a0\u00a0\u00a0 @ clean+invalidate D<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r1, c7, c5, 0\u00a0\u00a0\u00a0\u00a0 @ invalidate I+BTB<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r1, c7, c15, 0\u00a0\u00a0\u00a0\u00a0 @ clean+invalidate unified<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r1, c7, c10, 4\u00a0\u00a0\u00a0\u00a0 @ drain WB<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div>__armv7_mmu_cache_flush:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r10, c0, c1, 5\u00a0\u00a0\u00a0\u00a0 @ read ID_MMFR1<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 tst\u00a0\u00a0\u00a0\u00a0 r10, #0xf &lt;&lt; 16\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ hierarchical cache (ARMv7)<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 beq\u00a0\u00a0\u00a0\u00a0 hierarchical<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r10, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r10, c7, c14, 0\u00a0\u00a0\u00a0\u00a0 @ clean+invalidate D<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 iflush<\/div>\n<div>hierarchical:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 stmfd\u00a0\u00a0\u00a0\u00a0 sp!, {r0-r5, r7, r9-r11}<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 1, r0, c0, c0, 1\u00a0\u00a0\u00a0\u00a0 @ read clidr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ands\u00a0\u00a0\u00a0\u00a0 r3, r0, #0x7000000\u00a0\u00a0\u00a0\u00a0 @ extract loc from clidr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r3, r3, lsr #23\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ left align loc bit field<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 beq\u00a0\u00a0\u00a0\u00a0 finished\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ if loc is 0, then no need to clean<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r10, #0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ start clean at cache level 0<\/div>\n<div>loop1:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r2, r10, r10, lsr #1\u00a0\u00a0\u00a0\u00a0 @ work out 3x current cache level<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r1, r0, lsr r2\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ extract cache type bits from clidr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 and\u00a0\u00a0\u00a0\u00a0 r1, r1, #7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ mask of the bits for current cache only<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 cmp\u00a0\u00a0\u00a0\u00a0 r1, #2\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ see what cache we have at this level<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 blt\u00a0\u00a0\u00a0\u00a0 skip\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ skip if no cache, or just i-cache<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 2, r10, c0, c0, 0\u00a0\u00a0\u00a0\u00a0 @ select current cache level in cssr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r10, c7, c5, 4\u00a0\u00a0\u00a0\u00a0 @ isb to sych the new cssr&amp;csidr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 1, r1, c0, c0, 0\u00a0\u00a0\u00a0\u00a0 @ read the new csidr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 and\u00a0\u00a0\u00a0\u00a0 r2, r1, #7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ extract the length of the cache lines<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r2, r2, #4\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ add 4 (line length offset)<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldr\u00a0\u00a0\u00a0\u00a0 r4, =0x3ff<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ands\u00a0\u00a0\u00a0\u00a0 r4, r4, r1, lsr #3\u00a0\u00a0\u00a0\u00a0 @ find maximum number on the way size<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 clz\u00a0\u00a0\u00a0\u00a0 r5, r4\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ find bit position of way size increment<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldr\u00a0\u00a0\u00a0\u00a0 r7, =0x7fff<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ands\u00a0\u00a0\u00a0\u00a0 r7, r7, r1, lsr #13\u00a0\u00a0\u00a0\u00a0 @ extract max number of the index size<\/div>\n<div>loop2:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r9, r4\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ create working copy of max way size<\/div>\n<div>loop3:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orr\u00a0\u00a0\u00a0\u00a0 r11, r10, r9, lsl r5\u00a0\u00a0\u00a0\u00a0 @ factor way and cache number into r11<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 orr\u00a0\u00a0\u00a0\u00a0 r11, r11, r7, lsl r2\u00a0\u00a0\u00a0\u00a0 @ factor index number into r11<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r11, c7, c14, 2\u00a0\u00a0\u00a0\u00a0 @ clean &amp; invalidate by set\/way<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 subs\u00a0\u00a0\u00a0\u00a0 r9, r9, #1\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ decrement the way<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bge\u00a0\u00a0\u00a0\u00a0 loop3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 subs\u00a0\u00a0\u00a0\u00a0 r7, r7, #1\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ decrement the index<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bge\u00a0\u00a0\u00a0\u00a0 loop2<\/div>\n<div>skip:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r10, r10, #2\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ increment cache number<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 cmp\u00a0\u00a0\u00a0\u00a0 r3, r10<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bgt\u00a0\u00a0\u00a0\u00a0 loop1<\/div>\n<div>finished:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r10, #0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ swith back to cache level 0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 2, r10, c0, c0, 0\u00a0\u00a0\u00a0\u00a0 @ select current cache level in cssr<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldmfd\u00a0\u00a0\u00a0\u00a0 sp!, {r0-r5, r7, r9-r11}<\/div>\n<div>iflush:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r10, c7, c5, 0\u00a0\u00a0\u00a0\u00a0 @ invalidate I+BTB<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r10, c7, c10, 4\u00a0\u00a0\u00a0\u00a0 @ drain WB<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div>__armv5tej_mmu_cache_flush:<\/div>\n<div>1:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r15, c7, c14, 3\u00a0\u00a0\u00a0\u00a0 @ test,clean,invalidate D cache<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bne\u00a0\u00a0\u00a0\u00a0 1b<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c5, 0\u00a0\u00a0\u00a0\u00a0 @ flush I cache<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c10, 4\u00a0\u00a0\u00a0\u00a0 @ drain WB<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div>__armv4_mmu_cache_flush:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r2, #64*1024\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ default: 32K dcache size (*2)<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r11, #32\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ default: 32 byte line size<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r3, c0, c0, 1\u00a0\u00a0\u00a0\u00a0 @ read cache type<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 teq\u00a0\u00a0\u00a0\u00a0 r3, r6\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ cache ID register present?<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 beq\u00a0\u00a0\u00a0\u00a0 no_cache_id<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r1, r3, lsr #18<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 and\u00a0\u00a0\u00a0\u00a0 r1, r1, #7<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r2, #1024<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r2, r2, lsl r1\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ base dcache size *2<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 tst\u00a0\u00a0\u00a0\u00a0 r3, #1 &lt;&lt; 14\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ test M bit<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 addne\u00a0\u00a0\u00a0\u00a0 r2, r2, r2, lsr #1\u00a0\u00a0\u00a0\u00a0 @ +1\/2 size if M == 1<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r3, r3, lsr #12<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 and\u00a0\u00a0\u00a0\u00a0 r3, r3, #3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r11, #8<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r11, r11, lsl r3\u00a0\u00a0\u00a0\u00a0 @ cache line size in bytes<\/div>\n<div>no_cache_id:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bic\u00a0\u00a0\u00a0\u00a0 r1, pc, #63\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ align to longest cache line<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r2, r1, r2<\/div>\n<div>1:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldr\u00a0\u00a0\u00a0\u00a0 r3, [r1], r11\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ s\/w flush D cache<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 teq\u00a0\u00a0\u00a0\u00a0 r1, r2<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bne\u00a0\u00a0\u00a0\u00a0 1b<\/div>\n<div><\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r1, c7, c5, 0\u00a0\u00a0\u00a0\u00a0 @ flush I cache<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r1, c7, c6, 0\u00a0\u00a0\u00a0\u00a0 @ flush D cache<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r1, c7, c10, 4\u00a0\u00a0\u00a0\u00a0 @ drain WB<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div>__armv3_mmu_cache_flush:<\/div>\n<div>__armv3_mpu_cache_flush:<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r1, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c0, 0\u00a0\u00a0\u00a0\u00a0 @ invalidate whole cache v3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div><\/div>\n<div>\/*<\/div>\n<div>* Various debugging routines for printing hex characters and<\/div>\n<div>* memory, which again must be relocatable.<\/div>\n<div>*\/<\/div>\n<div>#ifdef DEBUG<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .type\u00a0\u00a0\u00a0\u00a0 phexbuf,#object \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*phexbuf\u662f\u4e00\u4e2a\u5bf9\u8c61*\/<\/div>\n<div>phexbuf:\u00a0\u00a0\u00a0\u00a0 .space\u00a0\u00a0\u00a0\u00a0 12 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u4fdd\u755912\u5b57\u8282\u957f\u5ea6*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 .size\u00a0\u00a0\u00a0\u00a0 phexbuf, . &#8211; phexbuf \u00a0 \u00a0 \u00a0 \u00a0\/*phexbuf\u5927\u5c0f\u4e3a\u5f53\u524d\u4f4d\u7f6e\u51cf\u6389phexbuf\u8d77\u59cb\u4f4d\u7f6e\uff0c\u537312\u5b57\u8282*\/<\/div>\n<div><\/div>\n<div>phex:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 adr\u00a0\u00a0\u00a0\u00a0 r3, phexbuf \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u8f93\u51fa\u5bc4\u5b58\u5668\u6570\u636e\uff0c\u53c2\u6570r0: \u9700\u8981\u8f93\u51fa\u7684\u503c\uff0cr1:\u4e3a\u8f93\u51fa\u5b57\u8282\u957f\u5ea6\uff0c\u4e00\u822c\u4e3a8\u5b57\u8282\uff0c\u6bd4\u5982\u8f93\u51faddddbbbb\u8fd9\u6837\u5b50\u768416\u8fdb\u5236\u6570\u636e\u5c31\u662f8\u5b57\u8282\u5b57\u7b26\u957f*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r2, #0<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 strb\u00a0\u00a0\u00a0\u00a0 r2, [r3, r1] \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u53d8\u6210\u5b57\u7b26\u4e32\uff0c\u5c31\u662f\u5b57\u7b26\u6570\u7ec4\u5c3e\u90e8\u52a0\u4e2a0*\/<\/div>\n<div>1:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 subs\u00a0\u00a0\u00a0\u00a0 r1, r1, #1 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u957f\u5ea6\u51cf1*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 movmi\u00a0\u00a0\u00a0\u00a0 r0, r3 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u957f\u5ea6\u4e3a\u8d1f\uff0c\u5219\u5904\u7406\u5b8c\u6210\uff0c\u628ar3\u5373phexbuf\u7684\u5730\u5740\u5b58\u5165r0\uff0c\u8c03\u7528puts\u8fdb\u884c\u8f93\u51fa*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bmi\u00a0\u00a0\u00a0\u00a0 puts<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 and\u00a0\u00a0\u00a0\u00a0 r2, r0, #15 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u957f\u5ea6\u8fd8\u6709\uff0c\u5219r2 = r0 &amp; 0x0f\uff0c\u5373\u5904\u7406\u6700\u4f4e4\u4f4d*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, r0, lsr #4 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*r0 = r0 &gt;&gt; 4*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 cmp\u00a0\u00a0\u00a0\u00a0 r2, #10 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*r2\u5c31\u662f\u6700\u4f4e4\u4f4d\u5927\u4e8e10\uff0c\u53730x0a,0x0b,&#8230;,0x0f\uff0c\u5219\u5148\u52a0\u4e00\u4e2a7\uff0c\u56e0\u4e3a&#8217;A&#8217;\u7684asc\u7801\u662f65\uff0c\u800c&#8217;0&#8217;\u662f48\uff0c\u4e24\u8005\u76f8\u5dee17\u3002*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 addge\u00a0\u00a0\u00a0\u00a0 r2, r2, #7<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r2, r2, #&#8217;0&#8242; \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u628a\u6570\u5b57\u52a0\u4e0a&#8217;0&#8217;\uff0c\u53d8\u6210ASCII\u7801*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 strb\u00a0\u00a0\u00a0\u00a0 r2, [r3, r1] \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u5b58\u5230phexbuf\u7684\u5c3e\u90e8\uff0c\u5c31\u662f\u4ece\u540e\u9762\u5f80\u524d\u4f9d\u6b21\u5199\u5165\u4f20\u5165\u7684r0\u7684\u5730\u4f4d\u5230\u9ad8\u4f4d\uff0c\u8fd9\u6837\u8f93\u51fa\u65f6\u5c31\u4f1a\u6b63\u8fc7\u6765\u3002*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 1b \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u7ee7\u7eed\u5904\u7406*\/<\/div>\n<div><\/div>\n<div>puts:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 loadsp\u00a0\u00a0\u00a0\u00a0 r3 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u8f93\u51fa\u5b57\u7b26\u4e32\uff0c\u628a\u8f93\u51fa\u7684\u6570\u636e\u7aef\u53e3\u653e\u5165r3\uff0c\u5f80r3\u5199\u5165\u6570\u636e\u5c31\u662f\u8f93\u51fa\u6570\u636e\u5230\u5916\u9762\uff0c\u6bd4\u5982\u8f93\u51fa\u5230UART*\/<\/div>\n<div>1:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldrb\u00a0\u00a0\u00a0\u00a0 r2, [r0], #1 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*r2 = r0\u5373\u4e0a\u9762\u7684phexbuf\u5730\u5740\u7684\u5b57\u7b26\uff0c\u7136\u540er0 = r0 + 1*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 teq\u00a0\u00a0\u00a0\u00a0 r2, #0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u5b57\u7b26\u4e32\u7ed3\u675f\uff0c\u6700\u540e\u4e00\u4e2a\u5b57\u8282\u4e3a0\uff0c\u5219\u8fd4\u56de*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 moveq\u00a0\u00a0\u00a0\u00a0 pc, lr<\/div>\n<div>2:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 writeb\u00a0\u00a0\u00a0\u00a0 r2, r3 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u628ar2\u8f93\u51fa*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r1, #0x00020000 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u7b49\u5f85\u8f93\u51fa\u5b8c\u6210*\/<\/div>\n<div>3:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 subs\u00a0\u00a0\u00a0\u00a0 r1, r1, #1<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bne\u00a0\u00a0\u00a0\u00a0 3b<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 teq\u00a0\u00a0\u00a0\u00a0 r2, #&#8217;\\n&#8217; \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u5982\u679c\u521a\u624d\u8f93\u51fa\u7684\u662f&#8217;\\n&#8217;\u5b57\u7b26\uff0c\u5219\u8ddf\u7740\u8f93\u51fa\u4e00\u4e2a&#8217;\\r&#8217;\u5b57\u7b26*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 moveq\u00a0\u00a0\u00a0\u00a0 r2, #&#8217;\\r&#8217;<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 beq\u00a0\u00a0\u00a0\u00a0 2b<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 teq\u00a0\u00a0\u00a0\u00a0 r0, #0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*r0\u5728putc\u65f6\u4e3a0\uff0c\u5728puts\u65f6\u4e0d\u4f1a\u4e3a0\uff0c\u6240\u4ee5\u8fd8\u662f\u4f1a\u8df3\u5230\u524d\u9762\u53bb\u8f93\u51fa\u5176\u5b83\u5b57\u7b26\u3002*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bne\u00a0\u00a0\u00a0\u00a0 1b<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 pc, lr \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*r0\u4e3a0\u5219\u8fd4\u56de*\/<\/div>\n<div>putc: \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u8f93\u51fa\u4e00\u4e2a\u5b57\u7b26*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r2, r0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*r2 \u4e3a\u5b57\u7b26*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*r0 \uff1d 0*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 loadsp\u00a0\u00a0\u00a0\u00a0 r3 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u8f7d\u5165\u8f93\u51fa\u7aef\u53e3r3*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 b\u00a0\u00a0\u00a0\u00a0 2b \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u8df3\u8f6c\u5230\u524d\u9762\u76842\u53f7\u6807\u7b7e\u5904\u6267\u884c*\/<\/div>\n<div><\/div>\n<div>memdump:\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r12, r0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u5185\u5b58dump\uff0c256bytes\uff0c\u53c2\u6570r0 \u4e3a\u8d77\u59cb\u5730\u5740*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r10, lr \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u4fdd\u5b58lr\uff0c\u8fd4\u56de\u7528*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r11, #0<\/div>\n<div>2:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, r11, lsl #2 \u00a0 \u00a0 \u00a0 \/*r0 \uff1d r11 &lt;&lt; 2*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r0, r0, r12 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*r0 = r0 + \u8d77\u59cb\u5730\u5740*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r1, #8 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*r1 \u4e3a\u957f\u5ea68*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 phex \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u8c03\u7528phex\u8f93\u51far0\u7684\u503c*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #&#8217;:&#8217;<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 putc \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u8f93\u51fa&#8217;:&#8217;*\/<\/div>\n<div>1:\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #&#8217; &#8216;<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 putc \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u8f93\u51fa\u7a7a\u683c*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 ldr\u00a0\u00a0\u00a0\u00a0 r0, [r12, r11, lsl #2] \u00a0 \/*\u8f93\u51fa\u5730\u5740\u6240\u5bf9\u5e94\u7684\u503c\uff0cr0\u4e3a\u8d77\u59cb\u5730\u5740+r11&lt;&lt;2\u6240\u5bf9\u5e94\u5730\u5740\u7684\u503c*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r1, #8 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u4e00\u6b21\u8f93\u51fa4\u5b57\u8282\u5185\u5bb9\uff0c\u663e\u793a8\u5b57\u8282\u7684\u5b57\u7b26*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bl\u00a0\u00a0\u00a0\u00a0 phex<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 and\u00a0\u00a0\u00a0\u00a0 r0, r11, #7 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*r0 = r11\u7684\u4f4e\u4e09\u4f4d*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 teq\u00a0\u00a0\u00a0\u00a0 r0, #3<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 moveq\u00a0\u00a0\u00a0\u00a0 r0, #&#8217; &#8216; \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*r0\u4e3a3\uff0c\u53734\u00d74\uff1d16\u5b57\u8282\uff0c\u5219\u8f93\u51fa\u591a\u4e00\u4e2a\u7a7a\u683c*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bleq\u00a0\u00a0\u00a0\u00a0 putc<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 and\u00a0\u00a0\u00a0\u00a0 r0, r11, #7<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 add\u00a0\u00a0\u00a0\u00a0 r11, r11, #1 \u00a0 \u00a0 \u00a0 \u00a0\/*r11 \u589e\u52a01*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 teq\u00a0\u00a0\u00a0\u00a0 r0, #7 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*r0 \u4e0d\u4e3a7\uff0c\u5373\u4e0d\u662f8*4=32\u5b57\u8282\u8fb9\u754c\uff0c\u8df3\u5230\u524d\u9762\u76841\u5904\u6267\u884c*\/<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 bne\u00a0\u00a0\u00a0\u00a0 1b<\/div>\n<div>\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 mov\u00a0\u00a0\u00a0\u00a0 r0, #&#8217;\\n&#8217; \u00a0 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