{"id":345,"date":"2018-03-14T09:43:50","date_gmt":"2018-03-14T01:43:50","guid":{"rendered":"http:\/\/www.max-shu.com\/blog\/?p=345"},"modified":"2018-03-14T09:43:50","modified_gmt":"2018-03-14T01:43:50","slug":"linux%e7%9a%84arch-arm-mm-proc-arch-s","status":"publish","type":"post","link":"http:\/\/www.max-shu.com\/blog\/?p=345","title":{"rendered":"linux\u7684arch\/arm\/mm\/proc-(arch).S"},"content":{"rendered":"
\u8fd9\u91cc\u4ee5arch\/arm\/mm\/proc-v6.S\u505a\u4f8b\u5b50\uff1a<\/div>\n
<\/div>\n
ENTRY(cpu_v6_proc_init)
\nmov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/p>\n

ENTRY(cpu_v6_proc_fin)
\nstmfd\u00a0\u00a0\u00a0\u00a0 sp!, {lr}
\ncpsid\u00a0\u00a0\u00a0\u00a0 if\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ disable interrupts
\nbl\u00a0\u00a0\u00a0\u00a0 v6_flush_kern_cache_all
\nmrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ ctrl register
\nbic\u00a0\u00a0\u00a0\u00a0 r0, r0, #0x1000\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ …i…………
\nbic\u00a0\u00a0\u00a0\u00a0 r0, r0, #0x0006\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ ………….ca.
\nmcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ disable caches
\nldmfd\u00a0\u00a0\u00a0\u00a0 sp!, {pc}<\/p>\n

\/*
\n*\u00a0\u00a0\u00a0\u00a0 cpu_v6_reset(loc)
\n*
\n*\u00a0\u00a0\u00a0\u00a0 Perform a soft reset of the system.\u00a0 Put the CPU into the
\n*\u00a0\u00a0\u00a0\u00a0 same state as it would be if it had been reset, and branch
\n*\u00a0\u00a0\u00a0\u00a0 to what would be the reset vector.
\n*
\n*\u00a0\u00a0\u00a0\u00a0 – loc\u00a0\u00a0 – location to jump to for soft reset
\n*
\n*\u00a0\u00a0\u00a0\u00a0 It is assumed that:
\n*\/
\n.align\u00a0\u00a0\u00a0\u00a0 5
\nENTRY(cpu_v6_reset)
\nmov\u00a0\u00a0\u00a0\u00a0 pc, r0<\/p>\n

\/*
\n*\u00a0\u00a0\u00a0\u00a0 cpu_v6_do_idle()
\n*
\n*\u00a0\u00a0\u00a0\u00a0 Idle the processor (eg, wait for interrupt).
\n*
\n*\u00a0\u00a0\u00a0\u00a0 IRQs are already disabled.
\n*\/
\nENTRY(cpu_v6_do_idle)
\nmcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r1, c7, c0, 4\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ wait for interrupt
\nmov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/p>\n

ENTRY(cpu_v6_dcache_clean_area)
\n#ifndef TLB_CAN_READ_FROM_L1_CACHE
\n1:\u00a0\u00a0\u00a0\u00a0 mcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c10, 1\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ clean D entry
\nadd\u00a0\u00a0\u00a0\u00a0 r0, r0, #D_CACHE_LINE_SIZE
\nsubs\u00a0\u00a0\u00a0\u00a0 r1, r1, #D_CACHE_LINE_SIZE
\nbhi\u00a0\u00a0\u00a0\u00a0 1b
\n#endif
\nmov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/p>\n

\/*
\n*\u00a0\u00a0\u00a0\u00a0 cpu_arm926_switch_mm(pgd_phys, tsk)
\n*
\n*\u00a0\u00a0\u00a0\u00a0 Set the translation table base pointer to be pgd_phys
\n*
\n*\u00a0\u00a0\u00a0\u00a0 – pgd_phys – physical address of new TTB
\n*
\n*\u00a0\u00a0\u00a0\u00a0 It is assumed that:
\n*\u00a0\u00a0\u00a0\u00a0 – we are not using split page tables
\n*\/
\nENTRY(cpu_v6_switch_mm)
\n#ifdef CONFIG_MMU
\nmov\u00a0\u00a0\u00a0\u00a0 r2, #0
\nldr\u00a0\u00a0\u00a0\u00a0 r1, [r1, #MM_CONTEXT_ID]\u00a0\u00a0\u00a0\u00a0 @ get mm->context.id
\norr\u00a0\u00a0\u00a0\u00a0 r0, r0, #TTB_FLAGS
\nmcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r2, c7, c5, 6\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ flush BTAC\/BTB
\nmcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r2, c7, c10, 4\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ drain write buffer
\nmcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c2, c0, 0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ set TTB 0
\nmcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r1, c13, c0, 1\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ set context ID
\n#endif
\nmov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/p>\n

\/*
\n*\u00a0\u00a0\u00a0\u00a0 cpu_v6_set_pte_ext(ptep, pte, ext)
\n*
\n*\u00a0\u00a0\u00a0\u00a0 Set a level 2 translation table entry.
\n*
\n*\u00a0\u00a0\u00a0\u00a0 – ptep\u00a0 – pointer to level 2 translation table entry
\n*\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \u00a0 (hardware version is stored at -1024 bytes)
\n*\u00a0\u00a0\u00a0\u00a0 – pte\u00a0\u00a0 – PTE value to store
\n*\u00a0\u00a0\u00a0\u00a0 – ext\u00a0\u00a0\u00a0\u00a0 – value for extended PTE bits
\n*\/
\narmv6_mt_table cpu_v6<\/p>\n

ENTRY(cpu_v6_set_pte_ext)
\n#ifdef CONFIG_MMU
\narmv6_set_pte_ext cpu_v6
\n#endif
\nmov\u00a0\u00a0\u00a0\u00a0 pc, lr<\/p>\n

cpu_v6_name:
\n.asciz\u00a0\u00a0\u00a0\u00a0 “ARMv6-compatible processor”
\n.align<\/p>\n

.section “.text.init”, #alloc, #execinstr<\/p>\n

\/*
\n*\u00a0\u00a0\u00a0\u00a0 __v6_setup
\n*
\n*\u00a0\u00a0\u00a0\u00a0 Initialise TLB, Caches, and MMU state ready to switch the MMU
\n*\u00a0\u00a0\u00a0\u00a0 on.\u00a0 Return in r0 the new CP15 C1 control register setting.
\n*
\n*\u00a0\u00a0\u00a0\u00a0 We automatically detect if we have a Harvard cache, and use the
\n*\u00a0\u00a0\u00a0\u00a0 Harvard cache control instructions insead of the unified cache
\n*\u00a0\u00a0\u00a0\u00a0 control instructions.
\n*
\n*\u00a0\u00a0\u00a0\u00a0 This should be able to cover all ARMv6 cores.
\n*
\n*\u00a0\u00a0\u00a0\u00a0 It is assumed that:
\n*\u00a0\u00a0\u00a0\u00a0 – cache type register is implemented
\n*\/
\n__v6_setup: \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*\u521d\u59cb\u5316v6\u5904\u7406\u5668\uff0cTLB\/CACHE\uff0c\u5207\u6362\u5230MMU on*\/
\n#ifdef CONFIG_SMP
\nmrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 1\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ Enable SMP\/nAMP mode
\norr\u00a0\u00a0\u00a0\u00a0 r0, r0, #0x20
\nmcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 1
\n#endif<\/p>\n

mov\u00a0\u00a0\u00a0\u00a0 r0, #0
\nmcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c14, 0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ clean+invalidate D cache \u00a0\/*\u6e05\u695acache\u3001buffer*\/
\nmcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c5, 0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ invalidate I cache
\nmcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c15, 0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ clean+invalidate cache
\nmcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c7, c10, 4\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ drain write buffer
\n#ifdef CONFIG_MMU
\nmcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c8, c7, 0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ invalidate I + D TLBs \u00a0 \u00a0 \u00a0\/*\u4f7f\u80fdTLB*\/
\nmcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c2, c0, 2\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ TTB control register
\norr\u00a0\u00a0\u00a0\u00a0 r4, r4, #TTB_FLAGS
\nmcr\u00a0\u00a0\u00a0\u00a0 p15, 0, r4, c2, c0, 1\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ load TTB1
\n#endif \/* CONFIG_MMU *\/
\nadr\u00a0\u00a0\u00a0\u00a0 r5, v6_crval \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u8bbe\u7f6e\u5904\u7406\u65b9\u6cd5v6_crval\uff0c\u770b\u4e0b\u9762*\/
\nldmia\u00a0\u00a0\u00a0\u00a0 r5, {r5, r6}
\nmrc\u00a0\u00a0\u00a0\u00a0 p15, 0, r0, c1, c0, 0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ read control register
\nbic\u00a0\u00a0\u00a0\u00a0 r0, r0, r5\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ clear bits them
\norr\u00a0\u00a0\u00a0\u00a0 r0, r0, r6\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ set them
\nmov\u00a0\u00a0\u00a0\u00a0 pc, lr\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 @ return to head.S:__ret \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u4ecehead.S\u7684 adr\u00a0\u00a0\u00a0\u00a0 lr, __enable_mmu \u77e5\u9053\uff0c\u6b64\u65f6lr\u4e3a__enable_mmu\uff0c\u5373\u8df3\u8f6c\u5230__enable_mmu\u5904\u6267\u884c\u3002*\/<\/p>\n

\/*
\n*\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 V X F\u00a0\u00a0 I D LR
\n* …. …E PUI. .T.T 4RVI ZFRS BLDP WCAM
\n* rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
\n*\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 0 110\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 0011 1.00 .111 1101 < we want
\n*\/
\n.type\u00a0\u00a0\u00a0\u00a0 v6_crval, #object \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*\u5728\u4e0a\u9762__v6_setup\u8bbe\u7f6e\u597d\u4f9b\u4ee5\u540e\u7528\u3002*\/
\nv6_crval:
\ncrval\u00a0\u00a0\u00a0\u00a0 clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c<\/p>\n

.type\u00a0\u00a0\u00a0\u00a0 v6_processor_functions, #object
\nENTRY(v6_processor_functions)
\n.word\u00a0\u00a0\u00a0\u00a0 v6_early_abort
\n.word\u00a0\u00a0\u00a0\u00a0 pabort_noifar
\n.word\u00a0\u00a0\u00a0\u00a0 cpu_v6_proc_init
\n.word\u00a0\u00a0\u00a0\u00a0 cpu_v6_proc_fin
\n.word\u00a0\u00a0\u00a0\u00a0 cpu_v6_reset
\n.word\u00a0\u00a0\u00a0\u00a0 cpu_v6_do_idle
\n.word\u00a0\u00a0\u00a0\u00a0 cpu_v6_dcache_clean_area
\n.word\u00a0\u00a0\u00a0\u00a0 cpu_v6_switch_mm
\n.word\u00a0\u00a0\u00a0\u00a0 cpu_v6_set_pte_ext
\n.size\u00a0\u00a0\u00a0\u00a0 v6_processor_functions, . – v6_processor_functions<\/p>\n

.type\u00a0\u00a0\u00a0\u00a0 cpu_arch_name, #object
\ncpu_arch_name:
\n.asciz\u00a0\u00a0\u00a0\u00a0 “armv6”
\n.size\u00a0\u00a0\u00a0\u00a0 cpu_arch_name, . – cpu_arch_name<\/p>\n

.type\u00a0\u00a0\u00a0\u00a0 cpu_elf_name, #object
\ncpu_elf_name:
\n.asciz\u00a0\u00a0\u00a0\u00a0 “v6”
\n.size\u00a0\u00a0\u00a0\u00a0 cpu_elf_name, . – cpu_elf_name
\n.align<\/p>\n

.section “.proc.info.init”, #alloc, #execinstr \u00a0 \/*\u53c2\u8003vmlinux.lds.S\uff0c\u53ef\u4ee5\u770b\u5230\u8fd9\u4e2a\u6bb5\u5bf9\u5e94__proc_info_begin\uff0c\u4ecehead-common.S\u77e5\u9053\uff0c__proc_info_begin\u662f\u7531__lookup_processor_type\u8fd9\u4e2a\u51fd\u6570\u8c03\u7528\uff0c\u4ece\u800c\u5f97\u5230\u5177\u4f53\u67d0\u4e2a\u5904\u7406\u5668\u7684\u4fe1\u606f\u3002<\/span>*\/<\/p>\n

\/*
\n* Match any ARMv6 processor core.
\n*\/
\n.type\u00a0\u00a0\u00a0\u00a0 __v6_proc_info, #object \u00a0 \u00a0 \u00a0\/*\u8fd9\u4e2a\u6bb5\u5c31\u5b9a\u4e49\u4e86\u8fd9\u4e2a\u7ed3\u6784\u4f53\uff0c\u5bf9\u5e94procinfo.h\u91cc\u9762\u7684proc_info_list\u7ed3\u6784*\/
\n__v6_proc_info:
\n.long\u00a0\u00a0\u00a0\u00a0 0x0007b000 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*cpu_val*\/
\n.long\u00a0\u00a0\u00a0\u00a0 0x0007f000 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*cpu_mask*\/
\n.long\u00a0\u00a0 PMD_TYPE_SECT | \\ \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*__cpu_mm_mmu_flags*\/
\nPMD_SECT_BUFFERABLE | \\
\nPMD_SECT_CACHEABLE | \\
\nPMD_SECT_AP_WRITE | \\
\nPMD_SECT_AP_READ
\n.long\u00a0\u00a0 PMD_TYPE_SECT | \\ \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*__cpu_io_mmu_flags*\/
\nPMD_SECT_XN | \\
\nPMD_SECT_AP_WRITE | \\
\nPMD_SECT_AP_READ
\nb\u00a0\u00a0\u00a0\u00a0 __v6_setup \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*__cpu_flush\uff0c\u770b\u4e0a\u9762\u7684__v6_setup*\/
\n.long\u00a0\u00a0\u00a0\u00a0 cpu_arch_name \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0\/*arch_name*\/
\n.long\u00a0\u00a0\u00a0\u00a0 cpu_elf_name \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*elf_name*\/
\n.long\u00a0\u00a0\u00a0\u00a0 HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA \u00a0 \/*elf_hwcap*\/
\n.long\u00a0\u00a0\u00a0\u00a0 cpu_v6_name \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*cpu_name*\/
\n.long\u00a0\u00a0\u00a0\u00a0 v6_processor_functions \u00a0 \u00a0 \u00a0 \/*proc*\/
\n.long\u00a0\u00a0\u00a0\u00a0 v6wbi_tlb_fns \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*tlb*\/
\n.long\u00a0\u00a0\u00a0\u00a0 v6_user_fns \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \/*user*\/
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